PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 528

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

asli
asr
asri
audio capture
audio codec 8-1,
audio in unit
audio input
audio memory format
audio out unit
audio sample rate
audio test
B
bandwidth
base address
BDATAAHIGH
BDATAALOW
BDATAMASK
BDATAVAL
BDCTL
BICTL
binary compatibility
BINSTHIGH
BINSTLOW
bit masking
bitand
bitandinv
bitinv
bitmap
bitor
bitxor
BIU_CTL
BIU_STATUS
blending
Index-2
A B C
A-10
A-9
A-11
diagnostic mode
memory data formats
memory data formats
requirements of ICP
PCI interface registers
picture
picture
picture
picture
picture
picture
picture
picture
masking
PCI interface MMIO register
picture
PCI interface MMIO register
picture
A-15
A-14
A-16
A-12
A-13
8-7
8-1
14-28
3-14
3-14
3-14
3-14
3-14
3-14
3-14
3-14
11-10
11-10
14-1
8-5
D
8-3
8-2
E
3-4
8-4
8-7
PRELIMINARY SPECIFICATION
F G
14-1
8-4
9-7
11-7
H
11-11
11-11
I
J
K
L M N O P Q R S
blending codes
block timing
boolean representation
borrow
boundary scan
breakpoints
built-in self test
byte ordering
bytesex
C
cache
alpha
alpha blendin
PCI output
PCI interface register
DSPCPU
address mapping,instruction cache
alignment 5-3,
associativity
bandwidth requirements
block siz
blocksize
byte in word
coherency 5-3, 5-4,
copyback
copyback operation
CPU stall
data cache characteristics,table
data cache initialization
data cache,description
dcb opcod
dinvalid opcode
dirty bit
dirty bits
dual port
endian-ness 5-3,
hidden concurrency
iclr operation
initialization
instruction cache
instruction cache coherency
instruction cache initialization and boot
instruction cache parameters
instruction cache summary
instruction cache tag
invalidate operation
latency
locking 5-3,
locking registers
LRU replacement
memory hole
A-17
3-2
14-1
3-13
5-8
5-4
5-3
e5-3
5-4
5-3
3-2
5-8
5-4
1-1
e5-6
14-16
5-4
5-8
5-3
5-3
5-9
5-5
g14-5
5-4
5-6
5-5
5-4
5-8
5-11
3-3
5-11
5-6
5-6
5-7
5-8
11-7
T U V W X Y
5-3
5-8
5-1
5-8
5-9
5-8
5-3
5-8
5-10
Z