PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 378

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

Philips Semiconductors
Invalidate all instruction cache blocks
SYNTAX
FUNCTION
DESCRIPTION
blocks.
included in the discard from the instruction cache, but i+3 will be retained.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
r10 = 0
r20 = 1
The
iclr
iclr
The side effect time behavior of
The
[ IF rguard ] iclr
if rguard then {
}
block
for all blocks in instruction cache {
}
iclr
icache_reset_valid_block(block)
block
iclr
does clear the valid bits of locked blocks.
ensures coherency between caches and main memory by discarding all pending prefetch operations.
0
operation resets the valid bits of all blocks in the instruction cache.
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
block + 1
Initial Values
iclr
is such that if instruction i performs an iclr, instructions i, i+1, i+2 will be
iclr
IF r10 iclr
IF r20 iclr
iclr
does not change the replacement status of instruction-cache
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
no change and no stall cycles, since
guard is false
dcb dinvalid
ATTRIBUTES
SEE ALSO
Result
branch
2, 3, 4
184
n/a
No
—
0
iclr
A-80