PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 454

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

Philips Semiconductors
Read program control and status word
SYNTAX
FUNCTION
DESCRIPTION
rdest. The layout of PCSW is shown below.
occur during program execution. Thus,
what events have occurred; this operation can also be used to save state before idling a task in a multi-tasking
environment.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
PCSW = 0x80110642
r20 = 0, PCSW = 0x80000000
r21 = 1, PCSW = 0x80000000
exception trap enable
Misaligned store exception
PCSW<31:16>
The
Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events that
The
[ IF rguard ] readpcsw
if rguard then {
}
PCSW<15:0>
Write back error trap enable
rdest
Misaligned store
readpcsw
readpcsw
Reserved exception
Write back error
Initial Values
PCSW
MSE
MSE
TRP
15
31
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
writes the current value of the PCSW (Program Control and Status Word) processor register to
Interrupt enable (1
WBE RSE
WBE
TRP
14
30
Count stalls (1
Reserved exception
trap enable
TRP
RSE
29
13
readpcsw
IF r20 readpcsw
IF r21 readpcsw
U N D E F
allow interrupts)
12
28
rdest
U N D E F
Yes)
readpcsw
CS
11
27
Operation
r100
TFE
IEN
10
26
Trap on first exit
can be used to determine current processor operating modes and
BSX IEEE MODE OFZ
25
9
r101
r102
U N D E F I N E D
Byte sex (1
PRELIMINARY SPECIFICATION
8
IEEE rounding mode
0
23
7
little endian)
r100
enabled, IEN=1 - interrupts enabled, BSX=1 - little
endian mode of operation, OFZ=1 - a denormalized
result was produced somewhere, INX=1 - an inexact
result was produced somewhere)
no change, since guard is false
r102
PNX1300/01/02/11 DSPCPU Operations
to nearest, 1
TRP
OFZ
22
6
0x80110642 (trap on MSE, INV and DBZ
0x80000000 (trap on MSE enabled)
TRP
IFZ
IFZ
21
5
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
to zero, 2
FP exception trap-enable bits
TRP
INV
INV
20
4
FP exceptions
Result
OVF
TRP
OVF
ATTRIBUTES
to positive, 3
19
writepcsw
3
SEE ALSO
readpcsw
UNF
TRP
UNF
18
2
TRP
INX
INX
to negative
17
1
fcomp
158
No
—
0
1
3
DBZ
TRP
DBZ
A-156
16
0