PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 529
PNX1311EH/G,557
Manufacturer Part Number
PNX1311EH/G,557
Description
IC MEDIA PROC 166MHZ 292-HBGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1300EHG557.pdf
(549 pages)
Specifications of PNX1311EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
48K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
169
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
292-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Other names
568-1295
935277721557
PNX1311EH/G
935277721557
PNX1311EH/G
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cache line size
carry
CCCOUNT
CCIR 656
CCIR 656 frame timing
CCIR 656 line timing
CCIR 656 pixel timing
CCIR656 serial D1
A B C
miss processing order 5-4,
miss transfer order
MMIO registers summary
noncachable region
non-cacheable region
number of sets
operation ordering
overview
overview,memory syste
parameters
partial word transfers
partial words
performance evaluation suppor
performance events
ports
rdstatus result format
rdtag result forma
replacement policies 5-3,
replacement policy
scheduling constraint
set
size
special data cache operations
special opcodes
special operation ordering
status operations 5-6,
summary of characteristics
tag field of address
tag operations 5-6,
valid bits
word in set
write misses
PCI interface register
definition
line timing
pixel timing
video connector on Enhanced Video Out
description
description table
picture
picture
A-18
5-3
table
description
description
5-3
5-3
7-5
7-5
D
5-3
5-1
Unit,picture
3-3
5-13
5-3
7-6
5-3
5-4
5-3
E
7-2
5-3
7-4
7-4
5-4
7-6
t5-6
5-7
F G
5-3
5-9
5-7
5-3
5-3
5-4
5-6
5-4
11-7
7-2
5-5
5-7
m5-1
5-4
5-13
5-7
5-9
5-2
H
5-6
t5-12
I
J
K
L M N O P Q R S
chroma
Chroma keying
chroma keying 14-1,
circuit board design
class code
Clipping
codec
coherency
coherency,instruction cache
command ID
compatibility
concurrency
concurrency,hidden
CONFIG_ADR
CONFIG_CTL
CONFIG_DATA
configuration header
configuration operations
control word
conversion
copyback
co-sited sampling
counter
CPU stall
curcycles
cycles
D
D1 serial
data address fields
data breakpoint
data cache
PRELIMINARY SPECIFICATION
keying
guidelines
PCI interface register
PCI interface register
software
PCI interface
PCI interface MMIO register
picture
PCI interface MMIO register
picture
PCI interface MMIO register
PCI interface
ICP vertical filter
of ICP
interspersed to co-sited
to RGB
to YUV composite
YUV to RGB 14-3,
coherency
dcb operatio
8-1
A-20
3-12
7-14
7-2
5-8
A-19
5-4
5-4
14-23
14-1
11-10
11-10
14-1
3-4
7-14
12-7
5-11
3-13
6-4
n5-6
11-3
11-2
5-3
5-7
14-9
11-3
14-25
14-1
14-9
11-6
11-3
T U V W X Y
5-9
7-11
11-12
11-13
11-13
Index-3
Z
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