PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 350

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

Philips Semiconductors
Floating-point compare less-than
pseudo-op for fgtr
SYNTAX
FUNCTION
DESCRIPTION
exchanged (
source files.)
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point operation but can only be reset by an explicit
occurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at the
same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
modification of the destination register. If the LSB of r guard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
The
[ IF rguard ] fles rsrc1 rsrc2
if rguard then {
}
if (float)rsrc1 < (float)rsrc2 then
else
flesflags
fles
rdest
rdest
fles
fles
Initial Values
fles
operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the second
operation is a pseudo operation transformed by the scheduler into an
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
1
0
’s rsrc1 is
operation computes the exception flags that would result from an individual
fgtr
’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
fles r30 r40
fles r30 r30
IF r10 fles r60 r30
IF r20 fles r60 r30
fles r30 r60
fles r30 r61
fles r50 r55
fles r60 r65
fles r50 r50
rdest
writepcsw
Operation
fles
r80
r90
r120
r121
r125
r126
r127
causes an IEEE exception, the corresponding exception
PRELIMINARY SPECIFICATION
operation. The update of the PCSW exception flags
r100
r110
PNX1300/01/02/11 DSPCPU Operations
r80
r90
no change, since guard is false
r110
r120
r121
r125
r126
r127
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
0
0
1
0
0, INV flag set
0
0, IFZ flag set
0
iles fgtr flesflags
readpcsw writepcsw
fgtr
ATTRIBUTES
SEE ALSO
Result
fles
with the arguments
.
fcomp
144
fles
No
—
2
1
3
A-52