PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 428

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

Philips Semiconductors
32-bit load with displacement
SYNTAX
FUNCTION
DESCRIPTION
in rdest. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4. If
the memory address computed by rsrc1 + d is not a multiple of 4, the result of
will be raised. This load operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xcfc,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
r30 = 0, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r40 = 1, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r50 = 0xd01
The
The
The
[ IF rguard ] ld32d(d) rsrc1
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
rdest<7:0>
rdest<15:8>
rdest<23:16>
rdest<31:24>
ld32d
ld32d
ld32d
bs
bs
Initial Values
3
0
ld32d
operation loads the 32-bit memory value from the address computed by rsrc1 + d and stores the result
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
mem[rsrc1 + d + (3
mem[rsrc1 + d + (2
mem[rsrc1 + d + (1
mem[rsrc1 + d + (0
has no side effects whatever.
bs)]
ld32d(4) r10
IF r30 ld32d(-8) r20
IF r40 ld32d(-8) r20
ld32d(-8) r50
bs)]
bs)]
bs)]
rdest
Operation
r60
r90
PRELIMINARY SPECIFICATION
r70
r80
PNX1300/01/02/11 DSPCPU Operations
r60
no change, since guard is false
r80
r90 undefined, since 0xd01 +(–8) is not a
multiple of 4
ld32d
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
0x84332211
0x48665544
ld32 ld32r ld32x st32
is undefined but no exception
st32d h_st32d
ATTRIBUTES
SEE ALSO
Result
–256..252 by 4
ld32d
ld32d
dmem
7 bits
4, 5
7
1
3
A-130
.