PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 356

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

Philips Semiconductors
Sign of floating-point value
SYNTAX
FUNCTION
DESCRIPTION
in rsrc1. rdest is set to 0 if r src1 is equal to zero, to 1 if r src1 is positive, or to –1 if rsrc1 is negative. The argument is
treated as an IEEE single-precision floating-point value; the result is an integer. If the argument is denormalized, zero
is substituted before computing the comparison, and the IFZ flag in the PCSW is set; thus, the result of
denormalized argument is 0. If
set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can
only be reset by an explicit
as rdest is written. If any other floating-point compute operations update the PCSW at the same time, the net result in
each exception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for that
exception flag.
modification of the destination register. If the LSB of r guard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0)
r40 = 0xbf800000 (-1.0)
r50 = 0x80800000 (-1.175494351e-38)
r60 = 0x80400000 (-5.877471754e-39)
r10 = 0, r70 = 0xffffffff (QNaN)
r20 = 1, r70 = 0xffffffff (QNaN)
r80 = 0xff800000 (-INF)
The
The
The
[ IF rguard ] fsign rsrc1
if rguard then {
}
if (float)rsrc1 = 0.0 then
else if (float)rsrc1 < 0.0 then
else
fsign
fsignflags
fsign
rdest
rdest
rdest
Initial Values
0
0xffffffff
1
operation sets the destination register, rdest, to either 0, 1, or –1 depending on the sign of the argument
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
writepcsw
fsign
fsign r30
fsign r40
fsign r50
fsign r60
IF r10 fsign r70
IF r20 fsign r70
fsign r80
causes an IEEE exception, the corresponding exception flags in the PCSW are
rdest
operation. The update of the PCSW exception flags occurs at the same time
Operation
r100
r105
r110
r115
r120
PRELIMINARY SPECIFICATION
r116
r117
PNX1300/01/02/11 DSPCPU Operations
r100
r105
r110
r115
no change, since guard is false
r117
r120
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
1
0xffffffff (-1)
0xffffffff (-1)
0, IFZ flag set
0, INV flag set
0xffffffff (-1)
fsignflags readpcsw
ATTRIBUTES
writepcsw
SEE ALSO
Result
fsign
fsign
.
fsign
fcomp
152
No
—
1
1
3
A-58
for a