LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 194

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when
Table 186. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1)
Table 187. UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when
DLAB = 0)
The U0IER is used to enable the four UART interrupt sources.
Table 188. UART Interrupt Enable Register (U0IER - address 0x4000 8004 when DLAB = 0) bit
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Bit
0
1
2
3
6:4
7
8
Symbol
DLLSB
Symbol
DLMSB
Symbol
RBRIE
THREIE
RXLIE
-
-
-
ABEOINTEN
bit description
DLAB = 1) bit description
description
All information provided in this document is subject to legal disclaimers.
Description
The UART Divisor Latch LSB Register, along with the U0DLM
register, determines the baud rate of the UART.
Reserved
Description
The UART Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UART.
Reserved
Value
Rev. 12 — 24 September 2012
0
1
0
1
0
1
0
1
-
-
Description
RBR Interrupt Enable. Enables the Receive Data Available
interrupt for UART. It also controls the Character Receive
Time-out interrupt.
Disable the RDA interrupt.
Enable the RDA interrupt.
THRE Interrupt Enable. Enables the THRE interrupt for
UART. The status of this interrupt can be read from
U0LSR[5].
Disable the THRE interrupt.
Enable the THRE interrupt.
RX Line Interrupt Enable. Enables the UART RX line
status interrupts. The status of this interrupt can be read
from U0LSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Reserved
Enables the end of auto-baud interrupt.
Disable end of auto-baud Interrupt.
Enable end of auto-baud Interrupt.
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x01
-
Reset value
0x00
-
194 of 538
Reset
value
0
0
0
-
NA
0
0