LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 498

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.6.2.3 Interrupt Clear-enable Register
28.6.2.4 Interrupt Set-pending Register
Table 442. ISER bit assignments
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
The ICER disables interrupts, and show which interrupts are enabled. See the register
summary in
The bit assignments are:
Table 443. ICER bit assignments
The ISPR forces interrupts into the pending state, and shows which interrupts are
pending. See the register summary in
The bit assignments are:
Table 444. ISPR bit assignments
Remark: Writing 1 to the ISPR bit corresponding to:
Bits
[31:0]
Bits
[31:0]
Bits
[31:0]
•
an interrupt that is pending has no effect
Name
SETENA
Table 28–440
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Name
CLRENA
Name
SETPEND
Rev. 12 — 24 September 2012
Function
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
for the register attributes.
Function
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Function
Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Table 28–440
for the register attributes.
UM10398
© NXP B.V. 2012. All rights reserved.
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