LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 222

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
14.6.4 SPI/SSP Status Register
14.6.5 SPI/SSP Clock Prescale Register
14.6.6 SPI/SSP Interrupt Mask Set/Clear Register
This read-only register reflects the current status of the SPI controller.
Table 211: SPI/SSP Status Register (SSP0SR - address 0x4004 000C, SSP1SR - address
This register controls the factor by which the Prescaler divides the SPI peripheral clock
SPI_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in the
SSPCR0 registers, to determine the bit clock.
Table 212: SPI/SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010, SSP1CPSR -
Important: the SSPnCPSR value must be properly initialized, or the SPI controller will not
be able to transmit data correctly.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI
peripheral clock selected in
relevant.
In master mode, CPSDVSR
This register controls whether each of the four possible interrupt conditions in the SPI
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Bit
0
1
2
3
4
31:5
Bit
7:0
31:8
RFF
BSY
Symbol
TFE
TNF
RNE
-
Symbol
CPSDVSR This even value between 2 and 254, by which SPI_PCLK is
-
0x4005 800C) bit description
address 0x4005 8010) bit description
All information provided in this document is subject to legal disclaimers.
Description
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Reserved.
Rev. 12 — 24 September 2012
Section
min
= 2 or larger (even numbers only).
3.5.15. The content of the SSPnCPSR register is not
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
0
-
Reset Value
1
0
0
0
NA
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