LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 489

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.6.1.4 Condition flags
28.5.6.1.5 Examples
28.5.7 Miscellaneous instructions
Remark: Bcond is the only conditional instruction on the Cortex-M0 processor.
These instructions do not change the flags.
Table 438
Table 438. Miscellaneous instructions
Mnemonic
BKPT
CPSID
CPSIE
DMB
DSB
ISB
MRS
MSR
NOP
SEV
•
B
BEQ labelD ; Conditionally branch to labelD if last flag setting
For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update
the EPSR T-bit and is discarded from the target address.
loopA ; Branch to loopA
BL
BX
BLX R0
; instruction set the Z flag, else do not branch.
shows the remaining Cortex-M0 instructions:
funC ; Branch with link (Call) to function funC, return address
LR
; stored in LR
; in R0
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
; Return from function call
; Branch with link and exchange (Call) to a address stored
Brief description
Breakpoint
Change Processor State, Disable Interrupts
Change Processor State, Enable Interrupts
Data Memory Barrier
Data Synchronization Barrier
Instruction Synchronization Barrier
Move from special register to register
Move from register to special register
No Operation
Send Event
Rev. 12 — 24 September 2012
UM10398
See
Section 28–28.5.7.
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Section 28–28.5.7.
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© NXP B.V. 2012. All rights reserved.
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