LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 450

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.4.1.3.6 Exception mask register
28.4.1.3.7 CONTROL register
Table 423. EPSR bit assignments
Attempts by application software to read the EPSR directly using the MRS instruction
always return zero. Attempts to write the EPSR using the MSR instruction are ignored.
Fault handlers can examine the EPSR value in the stacked PSR to determine the cause
of the fault. See
Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See
Section 28–28.4.4.1
Interruptible-restartable instructions:
and STM. When an interrupt occurs during the execution of one of these instructions, the
processor abandons execution of the instruction.
After servicing the interrupt, the processor restarts execution of the instruction from the
beginning.
The exception mask register disables the handling of exceptions by the processor.
Disable exceptions where they might impact on timing critical tasks or code sequences
requiring atomicity.
To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS
instruction, to change the value of PRIMASK. See
Section
Priority Mask Register:
configurable priority. See the register summary in
assignments are:
Table 424. PRIMASK register bit assignments
The CONTROL register controls the stack used when the processor is in Thread mode.
See the register summary in
Bits
[31:25]
[24]
[23:0]
Bits
[31:1]
[0]
•
•
•
instructions BLX, BX and POP{PC}
restoration from the stacked xPSR value on an exception return
bit[0] of the vector value on an exception entry.
28–28.5.7.7, and
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Section
Name
-
PRIMASK
Rev. 12 — 24 September 2012
for more information.
28–28.4.3.6. The following can clear the T bit to 0:
The PRIMASK register prevents activation of all exceptions with
Section 28–28.5.7.2
Table 28–419
-
T
-
Name
Function
Reserved
0 = no effect
1 = prevents the activation of all exceptions with
configurable priority.
The interruptible-restartable instructions are LDM
for its attributes. The bit assignments are:
for more information.
Table 28–419
Section
28–28.5.7.6,
Function
Reserved
Thumb state bit
Reserved
for its attributes. The bit
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