LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 387

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
22.7.2 Watchdog Timer Constant register
Table 343: Watchdog Mode register (WDMOD - 0x4000 4000) bit description
Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by
software. Both flags are cleared by an external reset or a Watchdog timer reset.
WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed
error occurs, or when WDPROTECT =1 and an attempt is made to write to the WDTC
register. This flag is cleared by software writing a 0 to this bit.
WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value
specified by WDWARNINT. This flag is cleared when any reset occurs, and is cleared by
software by writing a 1 to this bit.
Watchdog reset or interrupt will occur any time the watchdog is running. If a watchdog
interrupt occurs in Sleep mode, it will wake up the device.
Table 344. Watchdog operating modes selection
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. This is pre-loaded with the value
0x00 00FF upon reset. Writing values below 0xFF will cause 0x00 00FF to be loaded into
the WDTC. Thus the minimum time-out interval is T
If the WDPROTECT bit in WDMOD = 1, an attempt to change the value of WDTC before
the watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a
watchdog reset and set the WDTOF flag.
Bit
4
31:
5
WDEN
0
1
1
Symbol
WDPROTECT
-
WDRESET
X (0 or 1)
0
1
All information provided in this document is subject to legal disclaimers.
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
Value
0
1
Rev. 12 — 24 September 2012
Mode of Operation
Debug/Operate without the Watchdog running.
Watchdog interrupt mode: the watchdog warning interrupt will be
generated but watchdog reset will not. When this mode is selected, the
watchdog counter reaching the value specified by WDWARNINT will set
the WDINT flag and the Watchdog interrupt request will be generated.
Watchdog reset mode: both the watchdog interrupt and watchdog reset
are enabled. When this mode is selected, the watchdog counter reaching
the value specified by WDWARNINT will set the WDINT flag and the
Watchdog interrupt request will be generated, and the watchdog counter
reaching zero will reset the microcontroller. A watchdog feed prior to
reaching the value of WDWINDOW will also cause a watchdog reset.
Description
Watchdog update mode. This bit is Set Only.
The watchdog reload value (WDTC) can be changed
at any time.
The watchdog reload value (WDTC) can be changed
only after the counter is below the value of
WDWARNINT and WDWINDOW. Note: this mode is
intended for use only when WDRESET =1.
Reserved. Read value is undefined, only zero should
be written.
WDCLK
 256  4.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0
-
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