LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 480

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 435. ADC, ADD, RSB, SBC and SUB operand restrictions
UM10398
User manual
Instruction Rd
ADCS
ADD
ADDS
RSBS
SBCS
SUB
SUBS
28.5.5.1.3 Restrictions
28.5.5.1.4 Examples
28.5.5.2 AND, ORR, EOR, and BIC
R0-R7
R0-R15
R0-R7
SP
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
SP
R0-R7
R0-R7
R0-R7
See also
Table 435
be used with each instruction.
The following shows two instructions that add a 64-bit integer contained in R0 and R1 to
another 64-bit integer contained in R2 and R3, and place the result in R0 and R1.
64-bit addition:
Multiword values do not have to use consecutive registers. The following shows
instructions that subtract a 96-bit integer contained in R1, R2, and R3 from another
contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.
96-bit subtraction:
The following shows the RSBS instruction used to perform a 1's complement of a single
register.
Logical AND, OR, Exclusive OR, and Bit Clear.
Arithmetic negation:
ADDS R0, R0, R2 ; add the least significant words
SUBS R4, R4, R1 ; subtract the least significant words
Rn
R0-R7
R0-R15
SP or PC
SP
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
SP
R0-R7
R0-R7
R0-R7
ADCS R1, R1, R3 ; add the most significant words with carry
SBCS R5, R5, R2 ; subtract the middle words with carry
SBCS R6, R6, R3 ; subtract the most significant words with carry
Section
lists the legal combinations of register specifiers and immediate values that can
Rm
R0-R7
R0-PC
-
-
-
-
R0-R7
-
R0-R7
-
-
-
R0-R7
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
28–28.5.4.1.
Rev. 12 — 24 September 2012
-
0-7
0-255
-
-
-
0-7
0-255
-
imm
-
0-1020
0-508
0-508
RSBS R7, R7, #0 ; subtract R7 from zero
Restrictions
Rd and Rn must specify the same register.
Rd and Rn must specify the same register.
Rn and Rm must not both specify PC.
-
Rd and Rn must specify the same register.
-
-
Rd and Rn must specify the same register.
Immediate value must be an integer multiple of four.
-
Rd and Rn must specify the same register.
-
Immediate value must be an integer multiple of four.
Immediate value must be an integer multiple of four.
UM10398
© NXP B.V. 2012. All rights reserved.
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