LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 28

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.10 System PLL clock source update enable register
3.5.12 Main clock source update enable register
3.5.11 Main clock source select register
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 17.
This register selects the main system clock which can be either any input to the system
PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators
directly. The main system clock clocks the core, the peripherals, and the memories.
The MAINCLKUEN register (see
the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
Table 18.
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Bit
0
31:1
Bit
1:0
31:2
Symbol
ENA
-
Symbol
SEL
-
System PLL clock source update enable register (SYSPLLCLKUEN, address
0x4004 8044) bit description
Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
-
Value
0
1
-
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Input clock to system PLL
System PLL clock out
Description
Clock source for main clock
IRC oscillator
WDT oscillator
Reserved
Description
Enable system PLL clock source update
No change
Update clock source
Reserved
Section
3.5.12) must be toggled from LOW to HIGH for
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x00
0x00
Reset value
0x0
0x00
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