LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 219

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
14.6 Register description
Table 206. Register overview: SPI0 (base address 0x4004 0000)
Table 207. Register overview: SPI1 (base address 0x4005 8000)
UM10398
User manual
Name
SSP0CR0
SSP0CR1
SSP0DR
SSP0SR
SSP0CPSR
SSP0IMSC
SSP0RIS
SSP0MIS
SSP0ICR
Name
SSP1CR0
SSP1CR1
SSP1DR
SSP1SR
SSP1CPSR
SSP1IMSC
SSP1RIS
SSP1MIS
SSP1ICR
14.6.1 SPI/SSP Control Register 0
Access Address
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
WO
Access Address
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
WO
The register addresses of the SPI controllers are shown in
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Remark: Register names use the SSP prefix to indicate that the SPI controllers have full
SSP capabilities.
This register controls the basic operation of the SPI/SSP controller.
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
Description
Control Register 0. Selects the serial clock rate, bus type, and data size. 0
Control Register 1. Selects master/slave and other modes.
Data Register. Writes fill the transmit FIFO, and reads empty the receive
FIFO.
Status Register
Clock Prescale Register
Interrupt Mask Set and Clear Register
Raw Interrupt Status Register
Masked Interrupt Status Register
SSPICR Interrupt Clear Register
Description
Control Register 0. Selects the serial clock rate, bus type, and data size. 0
Control Register 1. Selects master/slave and other modes.
Data Register. Writes fill the transmit FIFO, and reads empty the receive
FIFO.
Status Register
Clock Prescale Register
Interrupt Mask Set and Clear Register
Raw Interrupt Status Register
Masked Interrupt Status Register
SSPICR Interrupt Clear Register
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
Table 206
and
UM10398
© NXP B.V. 2012. All rights reserved.
Table
207.
Reset
value
0
0
0x0000
0003
0
0
0x0000
0008
0
NA
Reset
value
0
0
0x0000
0003
0
0
0x0000
0008
0
NA
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