LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 267

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
15.11 Software example
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15.10.10 The state service routines
15.10.11 Adapting state services to an application
15.10.8 Initialization
15.10.9 I
15.11.1 Initialization routine
15.11.2 Start Master Transmit function
In the initialization example, the I
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
The I
Call. If the General Call or the own slave address is detected, an interrupt is requested
and STAT is loaded with the appropriate state information.
When the I
26 state services to be executed.
Each state routine is part of the I
The state service examples show the typical actions that must be performed in response
to the 26 I
associated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of time-out during I
operations, in order to trap an inoperative bus or a lost service routine.
Example to initialize I
Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then
initiating a START.
2
1. Load ADR with own Slave Address, enable General Call recognition if needed.
2. Enable I
3. Write 0x44 to CONSET to set the I2EN and AA bits, enabling Slave functions. For
1. Initialize Master data counter.
•
•
•
C interrupt service
ADR is loaded with the part’s own slave address and the General Call bit (GC)
The I
The slave mode is enabled by simultaneously setting the I2EN and AA bits in CON
and the serial clock frequency (for master modes) is defined by is defined by loading
the
Master only functions, write 0x40 to CONSET.
2
C hardware now begins checking the I
SCLH and SCLL registers
2
2
C interrupt enable and interrupt priority bits are set
2
C state codes. If one or more of the four I
C interrupt is entered, STAT contains a status code which identifies one of the
2
C interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
C Interface as a Slave and/or Master.
. The master routines must be started in the main program.
2
2
C interrupt routine and handles one of the 26 states.
C block is enabled for both master and slave modes.
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
C-bus for its own slave address and General
2
C operating modes are not used, the
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2
C