LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 246

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LPC1114FHN33/203,5

Manufacturer Part Number
LPC1114FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1114FHN33/203,5

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1114
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
NXP Semiconductors
UM10398
User manual
Fig 50. I
2
C serial interface block diagram
15.9.1 Input filters and output stages
SDA
SCL
status
bus
Input signals are synchronized with the internal clock, and spikes shorter than three
clocks are filtered out.
The output for I
OUTPUT
OUTPUT
FILTER
FILTER
STAGE
INPUT
STAGE
INPUT
DECODER
STATUS
2
All information provided in this document is subject to legal disclaimers.
C is a special pad designed to conform to the I
I2CnADDR0 to I2CnADDR3
ADDRESS REGISTERS
I2CnCONSET, I2CnCONCLR, I2CnSCLH, I2CnSCLL
MASK and COMPARE
Rev. 12 — 24 September 2012
ARBITRATION and
MONITOR MODE
SERIAL CLOCK
BIT COUNTER/
I2CnMMCTRL
GENERATOR
SYNC LOGIC
REGISTER
SCL DUTY CYLE REGISTERS
SHIFT REGISTER
CONTROL REGISTER and
STATUS REGISTER
I2CnDAT
I2CnSTAT
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
MATCHALL
I2CnMMCTRL[3]
I2CnMASK0 to I2CnMASK3
TIMING and
CONTROL
LOGIC
MASK REGISTERS
I2CnDATABUFFER
ACK
PCLK
interrupt
16
8
8
8
2
C specification.
UM10398
© NXP B.V. 2012. All rights reserved.
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