LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 524

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
29.5 Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. System PLL block diagram . . . . . . . . . . . . . . . . .49
Fig 11. Power profiles pointer structure . . . . . . . . . . . . . .56
Fig 12. LPC111x/102/202/302 clock configuration for power
Fig 13. Power profiles usage . . . . . . . . . . . . . . . . . . . . . .61
Fig 14. Standard I/O pin configuration . . . . . . . . . . . . . . .67
Fig 15. Standard I/O pin configuration . . . . . . . . . . . . . .101
Fig 16. Pin configuration LQFP48 package . . . . . . . . . .138
Fig 17. Pin configuration HVQFN33 package . . . . . . . .139
Fig 18. Pin configuration HVQFN24 package . . . . . . . .139
Fig 19. Pin configuration LQFP48 package . . . . . . . . . .140
Fig 20. Pin configuration (LPC11C22/C24) . . . . . . . . . .141
Fig 21. Pin configuration LQFP100 package . . . . . . . . .142
Fig 22. Pin configuration SO20 package . . . . . . . . . . . .161
Fig 23. Pin configuration TSSOP20 package with I
Fig 24. Pin configuration TSSOP20 package with V
Fig 25. Pin configuration TSSOP28 package . . . . . . . .167
Fig 26. Pin configuration DIP28 package. . . . . . . . . . . .167
Fig 27. Pin configuration LQFP48 package . . . . . . . . . .172
Fig 28. Pin configuration HVQFN33 package . . . . . . . .173
Fig 29. Masked write operation to the GPIODATA
Fig 30. Masked read operation . . . . . . . . . . . . . . . . . . .189
Fig 31. Auto-RTS Functional Timing . . . . . . . . . . . . . . .201
Fig 32. Auto-CTS Functional Timing . . . . . . . . . . . . . . .202
Fig 33. Auto-baud a) mode 0 and b) mode 1 waveform 207
Fig 34. Algorithm for setting UART dividers. . . . . . . . . .210
Fig 35. UART block diagram . . . . . . . . . . . . . . . . . . . . .216
Fig 36. Texas Instruments Synchronous Serial Frame
Fig 37. SPI frame format with CPOL=0 and CPHA=0 (a)
Fig 38. SPI frame format with CPOL=0 and CPHA=1 . .227
Fig 39. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 40. SPI Frame Format with CPOL = 1 and
Fig 41. Microwire frame format (single transfer) . . . . . .230
Fig 42. Microwire frame format (continuous transfers) .230
Fig 43. Microwire frame format setup and hold details .231
Fig 44. I
UM10398
User manual
LPC111x block diagram (LPC1100 and LPC1100L
series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LPC111x block diagram (LPC1100XL series) . . .12
LPC11Cxx/LPC11D14 block diagram (LPC1100C
series and LPC11D14). . . . . . . . . . . . . . . . . . . . .13
LPC11D14 block diagram . . . . . . . . . . . . . . . . . .14
PCF8576D block diagram . . . . . . . . . . . . . . . . . .14
LPC111x/LPC11Cxx memory map (LPC1100 and
LPC1100L series) . . . . . . . . . . . . . . . . . . . . . . . .17
LPC111x memory map (LPC1100XL series) . . . .18
LPC111x/LPC11Cxx CGU block diagram . . . . . .21
Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . .43
API use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
V
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .225
Single and b) Continuous Transfer) . . . . . . . . . .226
Single and b) Continuous Transfer) . . . . . . . . . .228
CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
2
SSA
C-bus configuration . . . . . . . . . . . . . . . . . . . . .233
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
DDA
C-bus
and
Fig 45. Format in the Master Transmitter mode . . . . . . 243
Fig 46. Format of Master Receiver mode . . . . . . . . . . . 244
Fig 47. A Master Receiver switches to Master Transmitter
Fig 48. Format of Slave Receiver mode . . . . . . . . . . . . 245
Fig 49. Format of Slave Transmitter mode . . . . . . . . . . 245
Fig 50. I
Fig 51. Arbitration procedure. . . . . . . . . . . . . . . . . . . . . 248
Fig 52. Serial clock synchronization . . . . . . . . . . . . . . . 248
Fig 53. Format and states in the Master Transmitter
Fig 54. Format and states in the Master Receiver
Fig 55. Format and states in the Slave Receiver mode 260
Fig 56. Format and states in the Slave Transmitter
Fig 57. Simultaneous Repeated START conditions from two
Fig 58. Forced access to a busy I
Fig 59. Recovering from a bus obstruction caused by a
Fig 60. C_CAN block diagram. . . . . . . . . . . . . . . . . . . . 276
Fig 61. CAN core in Silent mode. . . . . . . . . . . . . . . . . . 299
Fig 62. CAN core in Loop-back mode . . . . . . . . . . . . . . 300
Fig 63. CAN core in Loop-back mode combined with Silent
Fig 64. Block diagram of a message object transfer . . 302
Fig 65. Reading a message from the FIFO buffer to the
Fig 66. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Fig 67. CAN API pointer structure. . . . . . . . . . . . . . . . . 313
Fig 68. Sample PWM waveforms with a PWM cycle length
Fig 69. A timer cycle in which PR=2, MRx=6, and both
Fig 70. A timer cycle in which PR=2, MRx=6, and both
Fig 71. 16-bit counter/timer block diagram . . . . . . . . . . 338
Fig 72. Sample PWM waveforms with a PWM cycle length
Fig 73. A timer cycle in which PR=2, MRx=6, and both
Fig 74. A timer cycle in which PR=2, MRx=6, and both
Fig 75. 16-bit counter/timer block diagram . . . . . . . . . . 353
Fig 76. Sample PWM waveforms with a PWM cycle length
Fig 77. A timer cycle in which PR=2, MRx=6, and both
Fig 78. A timer cycle in which PR=2, MRx=6, and both
Fig 79. 32-bit counter/timer block diagram . . . . . . . . . . 367
Fig 80. A timer cycle in which PR=2, MRx=6, and both
after sending Repeated START . . . . . . . . . . . . 244
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . 266
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
message buffer . . . . . . . . . . . . . . . . . . . . . . . . . 308
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 337
interrupt and reset on match are enabled . . . . . 337
interrupt and stop on match are enabled . . . . . 337
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 351
interrupt and reset on match are enabled . . . . . 352
interrupt and stop on match are enabled . . . . . 352
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 366
interrupt and reset on match are enabled . . . . . 366
interrupt and stop on match are enabled . . . . . 366
2
C serial interface block diagram . . . . . . . . . . . 246
Chapter 29: Supplementary information
2
C-bus . . . . . . . . . . . 265
UM10398
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