LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 373

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 334: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
UM10398
User manual
Bit
0
1
2
Symbol Value Description
MR0I
MR0R
MR0S
bit description
21.7.4 Prescale Register (TMR32B0PR - address 0x4001 400C and
21.7.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and
21.7.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
1
0
1
0
1
0
TMR32B1PR - address 0x4001 800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 332: Prescale registers (TMR32B0PR, address 0x4001 400C and TMR32B1PR
TMR32B1PC - address 0x4001 8010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Table 333: Prescale counter registers (TMR32B0PC, address 0x4001 4010 and TMR32B1PC
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Bit
31:0
Bit
31:0
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
Enabled
Disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Enabled
Disabled
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Enabled
Disabled
Table
334.
Symbol
Symbol
PR
PC
0x4001 800C) bit description
0x4001 8010) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
Prescale value.
Description
Prescale counter value.
UM10398
© NXP B.V. 2012. All rights reserved.
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0
Reset
value
0
0
Reset
value
0
Reset
value
0