LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 376

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 338: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
UM10398
User manual
Bit
0
1
2
3
Symbol Value Description
EM0
EM1
EM2
EM3
bit description
21.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
21.7.9 Capture Register (TMR32B0CR0/1 - address 0x4001 402C/30 and
TMR32B1CR0/1 - address 0x4001 802C/30)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 337: Capture registers (TMR32B0CR0/1, addresses 0x4001 402C/30 and
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM outputs” on page
Bit
31:0
External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality
of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality
of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality
of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the
functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
Symbol
CAP
TMR32B1CR0/1, addresses 0x4001 802C/30) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
Timer counter capture value.
381).
(Section 21.8.2 “Rules for single edge
UM10398
© NXP B.V. 2012. All rights reserved.
376 of 538
Reset
value
0
Reset
value
0
0
0
0