LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 534

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
23.3
23.4
23.5
23.6
23.7
23.7.1
Chapter 24: LPC111x/LPC11Cxx System tick timer (SysTick)
24.1
24.2
24.3
24.4
24.5
24.5.1
24.5.2
Chapter 25: LPC111x/LPC11Cxx ADC
25.1
25.2
25.3
25.4
25.5
25.5.1
25.5.2
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
26.1
26.2
26.3
26.3.1
26.3.2
26.3.3
26.3.4
26.3.5
26.3.6
26.3.7
26.3.8
26.3.8.1
26.4
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.4.6
26.4.7
26.4.8
26.4.9
26.5
UM10398
User manual
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
WDT clocking . . . . . . . . . . . . . . . . . . . . . . . . . 392
Register description . . . . . . . . . . . . . . . . . . . 393
How to read this chapter . . . . . . . . . . . . . . . . 396
Basic configuration . . . . . . . . . . . . . . . . . . . . 396
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
General description . . . . . . . . . . . . . . . . . . . . 396
Register description . . . . . . . . . . . . . . . . . . . 397
How to read this chapter . . . . . . . . . . . . . . . . 400
Basic configuration . . . . . . . . . . . . . . . . . . . . 400
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 400
Register description . . . . . . . . . . . . . . . . . . . 401
How to read this chapter . . . . . . . . . . . . . . . . 406
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
General description . . . . . . . . . . . . . . . . . . . . 407
UART Communication protocol . . . . . . . . . . 415
UART ISP commands . . . . . . . . . . . . . . . . . . 416
Watchdog Mode register (WDMOD -
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 393
System Timer Control and status register . . 397
System Timer Reload value register . . . . . . 398
A/D Control Register (AD0CR - 0x4001
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
A/D Global Data Register (AD0GDR -
0x4001 C004) . . . . . . . . . . . . . . . . . . . . . . . . 403
Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Memory map after any reset. . . . . . . . . . . . . 408
Criterion for Valid User Code . . . . . . . . . . . . 408
Boot process flowchart . . . . . . . . . . . . . . . . . 410
Flash configuration for LPC1100, LPC1100C,
LPC1100L series . . . . . . . . . . . . . . . . . . . . . 411
Flash configuration for LPC1100XL series . . 411
Flash content protection mechanism . . . . . . 412
Code Read Protection (CRP) . . . . . . . . . . . . 412
ISP entry protection . . . . . . . . . . . . . . . . . . . 414
UART ISP command format . . . . . . . . . . . . . 415
UART ISP response format . . . . . . . . . . . . . 415
UART ISP data format . . . . . . . . . . . . . . . . . 415
UART ISP flow control . . . . . . . . . . . . . . . . . 415
UART SP command abort . . . . . . . . . . . . . . 415
Interrupts during UART ISP . . . . . . . . . . . . . 415
Interrupts during IAP. . . . . . . . . . . . . . . . . . . 416
RAM used by ISP command handler . . . . . . 416
RAM used by IAP command handler . . . . . . 416
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
23.7.2
23.7.3
23.7.4
23.8
24.5.3
24.5.4
24.6
24.7
25.5.3
25.5.4
25.5.5
25.6
25.6.1
25.6.2
25.6.3
26.5.1
26.5.2
26.5.3
26.5.4
26.5.5
26.5.6
26.5.7
26.5.8
26.5.9
26.5.10
26.5.11
26.5.12
26.5.13
26.5.14
26.5.15
26.6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 395
Functional description . . . . . . . . . . . . . . . . . 399
Example timer calculations . . . . . . . . . . . . . 399
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
C_CAN communication protocol. . . . . . . . . 425
Watchdog Timer Constant register (WDTC -
0x4000 4004) . . . . . . . . . . . . . . . . . . . . . . . . 394
Watchdog Feed register (WDFEED -
0x4000 4008) . . . . . . . . . . . . . . . . . . . . . . . . 394
Watchdog Timer Value register (WDTV -
0x4000 400C) . . . . . . . . . . . . . . . . . . . . . . . 395
System Timer Current value register . . . . . 398
System Timer Calibration value register
(SYST_CALIB - 0xE000 E01C) . . . . . . . . . . 399
Example (system clock = 50 MHz). . . . . . . . . 399
A/D Interrupt Enable Register (AD0INTEN -
0x4001 C00C) . . . . . . . . . . . . . . . . . . . . . . . 404
A/D Data Registers (AD0DR0 to AD0DR7 -
0x4001 C010 to 0x4001 C02C) . . . . . . . . . . 404
A/D Status Register (AD0STAT - 0x4001 C030) .
405
Hardware-triggered conversion . . . . . . . . . . 405
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Accuracy vs. digital receiver . . . . . . . . . . . . 405
Unlock <Unlock code> (UART ISP) . . . . . . . 417
Set Baud Rate <Baud Rate> <stop bit> (UART
ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Echo <setting> (UART ISP) . . . . . . . . . . . . . 417
Write to RAM <start address> <number of bytes>
(UART ISP) . . . . . . . . . . . . . . . . . . . . . . . . . 417
Read Memory <address> <no. of bytes> (UART
ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Prepare sector(s) for write operation <start sector
number> <end sector number> (UART ISP) 419
Copy RAM to flash <Flash address> <RAM
address> <no of bytes> (UART ISP) . . . . . . 419
Go <address> <mode> (UART ISP) . . . . . . 420
Erase sector(s) <start sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 421
Blank check sector(s) <sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 421
Read Part Identification number (UART ISP) 421
Read Boot code version number (UART ISP) 423
Compare <address1> <address2> <no of bytes>
(UART ISP) . . . . . . . . . . . . . . . . . . . . . . . . . 423
ReadUID (UART ISP) . . . . . . . . . . . . . . . . . 424
UART ISP Return Codes . . . . . . . . . . . . . . . 424
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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