LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 32

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.18 WDT clock source select register
3.5.19 WDT clock source update enable register
3.5.20 WDT clock divider register
Table 24.
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
(see
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 25.
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 26.
This register determines the divider values for the watchdog clock wdt_clk.
Bit
7:0
31:8
Bit
1:0
31:2
Bit
0
31:1
Section
Symbol
DIV
-
Symbol
SEL
-
Symbol
ENA
-
SPI1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description
WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit
description
WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)
bit description
3.5.19) must be toggled from LOW to HIGH for the update to take effect.
All information provided in this document is subject to legal disclaimers.
SPI1_PCLK clock divider values
Description
0: Disable SPI1_PCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Value
0x0
0x1
0x2
0x3
-
Value
0
1
-
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
WDT clock source
IRC oscillator
Main clock
Reserved
Description
Watchdog oscillator
Reserved
Description
Enable WDT clock source update
No change
Update clock source
Reserved
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x0
0x00
32 of 538
Reset
value
0x00
0x00
Reset
value
0x00
0x00