LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 413

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Table 371. Code Read Protection options
Table 372. Code Read Protection hardware/software interaction
Name
NO_ISP
CRP1
CRP2
CRP3
CRP option
None
None
None
CRP1
CRP1
CRP2
Pattern
programmed in
0x0000 02FC
0x4E69 7370
0x12345678
0x87654321
0x43218765
User Code
Valid
No
Yes
Yes
Yes
Yes
Yes
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
Description
Prevents sampling of pin PIO0_1 for entering ISP mode. PIO0_1 is
available for other uses.
Access to chip via the SWD pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. Since compare command
is disabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the flash.
Access to chip via the SWD pins is disabled. The following ISP
commands are disabled:
When CRP2 is enabled the ISP erase command only allows erasure
of all user sectors.
Access to chip via the SWD pins is disabled. ISP entry by pulling
PIO0_1 LOW is disabled if a valid user code is present in flash sector
0.
This mode effectively disables ISP override using PIO0_1 pin. It is up
to the user’s application to provide a flash update mechanism using
IAP calls or call reinvoke ISP command to enable flash update via
UART.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
•
•
•
•
•
•
•
•
•
•
PIO0_1 pin at
reset
x
High
Low
High
Low
High
Write to RAM command should not access RAM below 0x1000
0300. Access to addresses below 0x1000 0200 is disabled.
Copy RAM to flash command can not write to Sector 0.
Erase command can erase Sector 0 only when all sectors are
selected for erase.
Compare command is disabled.
Read Memory command is disabled.
Read Memory
Write to RAM
Go
Copy RAM to flash
Compare
SWD enabled LPC111x/
Yes
Yes
Yes
No
No
No
LPC11Cxx
enters ISP
mode
Yes
No
Yes
No
Yes
No
UM10398
© NXP B.V. 2012. All rights reserved.
partial flash
update in ISP
mode
Yes
NA
Yes
NA
Yes
NA
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