LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 404

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
25.5.3 A/D Interrupt Enable Register (AD0INTEN - 0x4001 C00C)
25.5.4 A/D Data Registers (AD0DR0 to AD0DR7 - 0x4001 C010 to
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 365. A/D Interrupt Enable Register (AD0INTEN - address 0x4001 C00C) bit description
0x4001 C02C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 366. A/D Data Registers (AD0DR0 to AD0DR7 - addresses 0x4001 C010 to
Bit
7:0
8
31:9 -
Bit
5:0
15:6
29:16 -
30
31
Symbol
ADINTEN
ADGINTEN
Symbol
-
V_VREF
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
DONE
0x4001 C02C) bit description
All information provided in this document is subject to legal disclaimers.
Description
Reserved.
When DONE is 1, this field contains a binary fraction representing the
voltage on the ADn pin, divided by the voltage on the V
the field indicates that the voltage on the ADn pin was less than, equal
to, or close to that on V
AD input was close to, equal to, or greater than that on V
Reserved.
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits.This bit is cleared by reading this
register.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
Description
These bits allow control over which A/D channels generate
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 7:0 will generate interrupts.
Remark: This bit must be set to 0 in burst mode (BURST = 1 in the
AD0CR register).
Reserved. Unused, always 0.
Rev. 12 — 24 September 2012
REF
, while 0x3FF indicates that the voltage on
Chapter 25: LPC111x/LPC11Cxx ADC
REF
UM10398
REF
© NXP B.V. 2012. All rights reserved.
pin. Zero in
.
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Reset
Value
0x00
1
0
Reset
Value
0
NA
0
0
0