LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 455

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.4.2.4 Software ordering of memory accesses
Table 426. Memory access behavior
[1]
The Code, SRAM, and external RAM regions can hold programs.
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
Section 28–28.4.2.2
of memory accesses. Otherwise, if the order of memory accesses is critical, software
must include memory barrier instructions to force that ordering. The processor provides
the following memory barrier instructions:
DMB — The Data Memory Barrier (DMB) instruction ensures that outstanding memory
transactions complete before subsequent memory transactions. See
DSB — The Data Synchronization Barrier (DSB) instruction ensures that outstanding
memory transactions complete before subsequent instructions execute. See
Section
ISB — The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent instructions. See
Section
The following are examples of using memory barrier instructions:
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
•
•
•
See
the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence
memory or devices in the memory map might have different wait states
some memory accesses are buffered or speculative.
Section 28–28.4.2.1
28–28.5.7.4.
28–28.5.7.5.
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private Peripheral
Bus
Device
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
describes the cases where the memory system guarantees the order
Rev. 12 — 24 September 2012
for more information.
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-ordered
Device
[1]
XN
-
-
XN
-
XN
XN
XN
[1]
Description
Executable region for program
code. You can also put data here.
Executable region for data. You
can also put code here.
External device memory.
Executable region for data.
External device memory.
This region includes the NVIC,
System timer, and System Control
Block. Only word accesses can be
used in this region.
Vendor specific.
Section
UM10398
© NXP B.V. 2012. All rights reserved.
28–28.5.7.3.
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