LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 359

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 318: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
UM10398
User manual
Bit
0
1
2
3
4
5
6
7
8
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
bit description
20.7.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 317: Prescale counter registers (TMR32B0PC, address 0x4001 4010 and TMR32B1PC
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Bit
31:0
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
Enabled
Disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Enabled
Disabled
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Enabled
Disabled
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
Enabled
Disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Enabled
Disabled
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Enabled
Disabled
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
Enabled
Disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Enabled
Disabled
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Enabled
Disabled
Table
318.
Symbol
PC
0x4001 8010) bit description
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Prescale counter value.
UM10398
© NXP B.V. 2012. All rights reserved.
359 of 538
0
0
0
Reset
value
0
0
0
0
0
0
Reset
value
0