LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 34

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.23 CLKOUT clock divider register
3.5.24 POR captured PIO status register 0
3.5.25 POR captured PIO status register 1
This register determines the divider value for the clock output signal on the CLKOUT pin.
Table 30.
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports
0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state
of one GPIO pin. This register is a read-only status register.
Table 31.
The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2
(PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of
one PIO pin. This register is a read-only status register.
Table 32.
Bit
7:0
31:8
Bit
11:0
23:12
31:24
Bit
0
1
2
3
4
5
6
7
8
9
31:10
Symbol
DIV
-
Symbol
CAPPIO0_n
CAPPIO1_n
CAPPIO2_n
Symbol
CAPPIO2_8
CAPPIO2_9
CAPPIO2_10
CAPPIO2_11
CAPPIO3_0
CAPPIO3_1
CAPPIO3_2
CAPPIO3_3
CAPPIO3_4
CAPPIO3_5
-
CLKOUT clock divider registers (CLKOUTCLKDIV, address 0x4004 80E8) bit
description
POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit
description
POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit
description
All information provided in this document is subject to legal disclaimers.
Clock output divider values
Description
0: Disable CLKOUT.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Description
Raw reset status input PIO0_n:
PIO0_11 to PIO0_0
Raw reset status input PIO1_n:
PIO1_11 to PIO1_0
Raw reset status input PIO2_n:
PIO2_7 to PIO2_0
Description
Raw reset status input PIO2_8
Raw reset status input PIO2_9
Raw reset status input PIO2_10
Raw reset status input PIO2_11
Raw reset status input PIO3_0
Raw reset status input PIO3_1
Raw reset status input PIO3_2
Raw reset status input PIO3_3
Raw reset status input PIO3_4
Raw reset status input PIO3_5
Reserved
Reset value
User implementation dependent
User implementation dependent
User implementation dependent
Reset value
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
User implementation dependent
-
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x00
0x00
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