LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 69

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
7.4 Register description
Table 55.
UM10398
User manual
Name
IOCON_PIO2_6
-
IOCON_PIO2_0
IOCON_RESET_PIO0_0
IOCON_PIO0_1
IOCON_PIO1_8
-
IOCON_PIO0_2
IOCON_PIO2_7
IOCON_PIO2_8
IOCON_PIO2_1
IOCON_PIO0_3
IOCON_PIO0_4
Register overview: I/O configuration (base address 0x4004 4000)
7.3.6 Open-drain Mode
When output is selected, either by selecting a special function in the FUNC field, or by
selecting GPIO function for a pin having a 1 in its GPIODIR register, a 1 in the OD bit
selects open-drain operation, that is, a 1 disables the high-drive transistor. This option has
no effect on the primary I
Remark: The open-drain mode is not available on all parts (see
The I/O configuration registers control the PIO port pins, the inputs and outputs of all
peripherals and functional blocks, the I
Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and
electrical characteristics.
Some input functions (SCK0, DSR, DCD, and RI) are multiplexed to several physical pins.
The IOCON_LOC registers select the pin location for each of these functions.
Remark: The IOCON registers are listed in order of their memory locations in
which correspond to the order of their physical pin numbers in the LQFP48 package
starting at the upper left corner with pin 1 (PIO2_6). See
registers ordered by port number.
The IOCON location registers are used to select a physical pin for multiplexed functions.
Remark: Note that once the pin location has been selected, the function still must be
configured in the corresponding IOCON registers for the function to be usable on that pin.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Address
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
Rev. 12 — 24 September 2012
2
C pins.
Description
I/O configuration for pin PIO2_6
Reserved
I/O configuration for pin
PIO2_0/DTR/SSEL1
I/O configuration for pin RESET/PIO0_0 0xD0
I/O configuration for pin
PIO0_1/CLKOUT/CT32B0_MAT2
I/O configuration for pin
PIO1_8/CT16B1_CAP0
Reserved
I/O configuration for pin
PIO0_2/SSEL0/CT16B0_CAP0
I/O configuration for pin PIO2_7
I/O configuration for pin PIO2_8
I/O configuration for pin
PIO2_1/DSR/SCK1
I/O configuration for pin PIO0_3
I/O configuration for pin PIO0_4/SCL
2
C-bus pins, and the ADC input pins.
Table 56
Section
for a listing of IOCON
Reset
value
0xD0
-
0xD0
0xD0
0xD0
-
0xD0
0xD0
0xD0
0xD0
0xD0
0x00
UM10398
© NXP B.V. 2012. All rights reserved.
7.1).
Reference
Table 57
-
Table 58
Table 59
Table 60
Table 61
-
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table
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55,