LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 502

• Manufacturer Part Number: LPC1114FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.6.3.1 The CMSIS mapping of the Cortex-M0 SCB registers
28.6.3.2 CPUID Register
28.6.3.3 Interrupt Control and State Register
Table 448. Summary of the SCB registers
[1]
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the array SHP[1] corresponds to the registers SHPR2-SHPR3.
The CPUID register contains the processor part number, version, and implementation
information. See the register summary in for its attributes. The bit assignments are:
Table 449. CPUID register bit assignments
The ICSR:
Address
0xE000ED00
0xE000ED04
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED1C
0xE000ED20
Bits
[31:24]
[23:20]
[19:16]
[15:4]
[3:0]
•
•
See the register description for more information.
provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
indicates:
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
Name
CPUID
ICSR
AIRCR
SCR
CCR
SHPR2
SHPR3
Name
Implementer
Variant
Constant
Partno
Revision
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Type
RO
RW
RW
RW
RO
RW
RW
[1]
[1]
Function
Implementer code:
0x41 = ARM
Variant number, the r value in the rnpn product revision
identifier:
0x0 = Revision 0
Constant that defines the architecture of the processor:, reads
as
0xC = ARMv6-M architecture
Part number of the processor:
0xC20 = Cortex-M0
Revision number, the p value in the rnpn product revision
identifier:
0x0 = Patch 0
Reset value
0x410CC200
0x00000000
0xFA050000
0x00000000
0x00000204
0x00000000
0x00000000
Description
Section 28.6.3.2
Section 28–28.6.3.3
Section 28–28.6.3.4
Section 28–28.6.3.5
Section 28–28.6.3.6
Section 28–28.6.3.7.1
Section 28–28.6.3.7.2
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