AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 186

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.7.1
Register Name:
Access Type:
Reset Value:
• MODE: SDRAMC Command Mode
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
Table 22-9.
186
0
0
0
0
1
1
1
MODE
31
23
15
–
–
–
7
–
0
0
1
1
0
0
1
AT91CAP7E
SDRAMC Mode Register
0
1
0
1
0
1
0
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the
cycle.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The address offset with respect to the SDRAM device base address is used to
program the Mode Register. For instance, when this mode is activated, an access to the “SDRAM_Base +
offset” address generates a “Load Mode Register” command with the value “offset” written to the SDRAM
device Mode Register.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed
regardless of the cycle. Previously, an “All Banks Precharge” command must be issued.
The SDRAM Controller issues an extended load mode register command when the SDRAM device is
accessed regardless of the cycle. The address offset with respect to the SDRAM device base address is
used to program the Mode Register. For instance, when this mode is activated, an access to the
“SDRAM_Base + offset” address generates an “Extended Load Mode Register” command with the value
“offset” written to the SDRAM device Mode Register.
Deep power-down mode. Enters deep power-down mode.
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
SDRAMC_MR
Read/Write
0x00000000
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
8549A–CAP–10/08
24
16
–
–
8
–
0