AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 440

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 31-10. Bank Swapping in Data OUT Transfers for Ping-pong EndpointsWhen using a ping-pong endpoint, the fol-
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AT91CAP7E
lowing procedures are required to perform Data OUT transactions:
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
Microcontroller
Write and Read at the Same Time
During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be
able to guarantee a constant bandwidth, the microcontroller must read the previous data pay-
load sent by the host, while the current data payload is received by the USB device. Thus two
banks of memory are used. While one is available for the microcontroller, the other one is locked
by the USB device.
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO
3. The USB device sends an ACK PID packet to the host. The host can immediately send
4. The microcontroller is notified that the USB device has received a data payload, polling
5. The number of bytes available in the FIFO is made available by reading RXBYTECNT
6. The microcontroller transfers out data received from the endpoint’s memory to the
7. The microcontroller notifies the USB peripheral device that it has finished the transfer
8. A third Data OUT packet can be accepted by the USB peripheral device and copied in
9. If a second Data OUT packet has been received, the microcontroller is notified by the
10. The microcontroller transfers out data received from the endpoint’s memory to the
Bank 0.
a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1.
RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this
endpoint while RX_DATA_BK0 is set.
in the endpoint’s UDP_ CSRx register.
microcontroller’s memory. Data received is made available by reading the endpoint’s
UDP_ FDRx register.
by clearing RX_DATA_BK0 in the endpoint’s UDP_ CSRx register.
the FIFO Bank 0.
flag RX_DATA_BK1 set in the endpoint’s UDP_ CSRx register. An interrupt is pending
for this endpoint while RX_DATA_BK1 is set.
microcontroller’s memory. Data received is available by reading the endpoint’s UDP_
FDRx register.
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
USB Device
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
USB Bus
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
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