AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 29

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.14
9.15
8549A–CAP–10/08
Chip Identification
PIO Controllers
• Debug Communication Channel Support
• Chip ID: 83770904 (0x1000 0011 0111 0111 0000 1001 0000 0100). This value is stored in
• JTAG ID: unique for each CAP7 personalization.
• Two PIO Controllers (PIOA and PIOB) included.
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
• Synchronous output, provides Set and Clear of several I/O lines in a single write
• PIOA has multiplexing of two peripheral functions per I/O Line (see section
• PIOB multiplexing is controlled by the FPGA Interface (see section
the Chip ID Register (DBGU_CIDR) in the Debug Unit. The last 5 bits of the register are
reserved for a chip version number.
Controller A Multiplexing” on page
Multiplexing” on page
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
– PIOA controls 32 I/O Lines (PA0 - PA31)
– PIOB can control up to 32 of the MPIO Lines
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
the ARM Processor’s ICE Interface
47)
36)
11.4.2 ”PIO Controller B
AT91CAP7E
10.4.1 ”PIO
29