AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 413

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

30.6
Table 30-4.
Table 30-5.
Notes:
8549A–CAP–10/08
Offset
0xC0
0xC4
Offset
0x00
0x40
0x80
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0xFC
Timer Counter (TC) User Interface
1. Read-only if WAVE = 0
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
TC Global Memory Map
TC Channel Memory Map
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Reserved
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC
block. TC channels are controlled by the registers listed in
channel registers in
tioned in
Table
30-5.
Table 30-5
is in relation to the offset of the corresponding channel as men-
TC_CMR
TC_CCR
TC_IMR
TC_IER
TC_IDR
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
TC_BCR
TC_BMR
Name
Name
–
See
See
See
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Access
Access
Table 30-5
Table 30-5
Table 30-5
Table
–
30-5. The offset of each of the
(1)
(1)
AT91CAP7E
Reset Value
Reset Value
–
0
–
–
0
0
0
0
0
–
–
0
–
–
0
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