AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 46

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.4
11.4.1
46
Programmability Options
AT91CAP7E
Mode-Bits
Table 11-1.
Mode-Bit
0
1
2
3
4
5
6
7
Mode-bits description
•
•
•
•
An approximation formula for the access time, from the ARM inside the CAP7E to the pe-
ripherals in the FPGA is shown below:
Inside the FPGA, the module called “CAP7E Control”, produces a reset and provides the dif-
ferent modes under reset conditions for the CAP7E. The RTL provided by ATMEL lets the
user configure their FPGA interface. By default, all mode bits are zeroes.
The following table shows the description and value for the emulation/modes bits supported
by CAP7E.
t3: Time for FPGA-Peripheral response
t4: Time to transfer response back to CAP7E (4 cycles single AHB interface, 8 cycles
dual AHB interface)
t5: Time to read back the response/data from FPGA to the internal CAP7E AHB bus
t6: Time for introduced wait cycles
CAP7 in ARM MODE
used for emulation of
used for emulation of
Slave mode select 2
Internal ROM select
Master mode select
Slave mode select 1
ADC / LVDS Select
PIOB mode select
Disable Pullups
Description
CAP7 only
CAP7 only
T
access
= t1 + t2 + t3 + t4 + t5
Single Master Mode
- use only Master A
SlaveC Mode - use
SlaveA Mode - use
Use internal ROM
CAP7E mode
Use Pull-Ups
only Slave C
only Slave A
Use PIOB
Use ADC
0
PDC, and APB bridge
SlaveC-D Mode - use
SlaveA-B Mode - use
use Masters A and B
Dual Master Mode -
CAP7-ARM emula-
Use external ZBT
Use FPIF IRQ’s,
Slaves C and D
Disable-Pullups
Slaves A and B
Use LVDS
tion mode
1
8549A–CAP–10/08