AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 52

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.6
11.6.1
Figure 11-9. EBI driving the FPGA
11.6.2
52
Interfacing using EBI
AT91CAP7E
EBI-FPGA Connections
EBI TIming
ARM Microcontroller
System
ARM
EBI SRAM
Controller
Using the GCC compiler with maximum optimization and assuming t2 (wait for FPGA re-
sponse ready) is also around 25 AHB cycles, and the system takes approximately 85 AHB
cycles for a read operation from the FPGA.
The External Bus Interface (EBI) module, is designed to transfer data between external de-
vices and the Memory Controllers of an ARM based device. These external Memory Con-
trollers are capable of handling several types of external memory and peripheral devices,
such as SDRAM, SRAM, NOR Flash, NAND Flash, and various PROM devices.
However, the EBI can also provide an interface to an FPGA as long as the FPGA can work
with one of the predefined memory interfaces. Due to its simplicity and familiarity, the Static
Memory Controller (SMC) which supports an SRAM-type interface is preferred for this pur-
pose. Usually the FPGA will have to include a module that understands the SMC timing and
is able to respond to the SMC as expected.
The EBI interface already provides all the necessary parallel, high-drive I/O to allow a user
to communicate with an FPGA with reasonable performance. However if the external device
is slow or introduces wait cycles, the throughput of the interface could be compromised. Also
since the EBI must be driven by the processor or another AHB master, the bandwidth that
the EBI can achieve is partly determined by the software that sets the bus and interrupt pri-
orities, etc.
Figure 11-9
interface is the SMC. A special module need to be designed in the FPGA to interface the
EBI-SMC to the CAP7E microcontroller.
Figure 11-10
and
NOTE
Figure 11-11
These timing diagrams are also shown in section TBD. All parameters shown are
programmable based on the speed of the external FPGA.
shows the ARM Microcontroller driving the FPGA through the EBI. The selected
shows the standard read timing for the EBI using the SMC memory interface
shows the standard write cycle.
Address
NWE
Data
NBS
NCS
NRD
FPGA
Logic
FPGA
8549A–CAP–10/08