AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 492

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 33-23. SMC Read Signals - NCS Controlled (READ_MODE= 0)
33.10.4.3
Table 33-24. SMC Write Signals - NWE controlled (WRITE_MODE = 1)
Notes:
Table 33-25. SMC Write NCS Controlled (WRITE_MODE = 0)
492
SMC
SMC
SMC
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
Symbol
SMC
SMC
SMC
12
13
14
15
16
17
18
19
20
21
22
23
24
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold
AT91CAP7E
length”.
A2 - A25 valid before NCS High
NRD low before NCS High
NCS Pulse Width
Write Timings
Parameter
Data Out Valid before NWE High
NWE Pulse Width
NBS0/A0 NBS1, NBS2/A1, NBS3,
A2 - A25 valid before NWE low
NCS low before NWE high
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25
change
NWE High to NCS Inactive
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25,
NCS change
Parameter
Data Out Valid before NCS High
NCS Pulse Width
NBS0/A0 NBS1, NBS2/A1, NBS3, A2 -
A25 valid before NCS low
NBS0/A0, NBS1, NBS2/A1, NBS3,
HOLD or NO HOLD SETTINGS (nwe hold … 0, nwe hold = 0)
(1)
NO HOLD SETTINGS (nwe hold = 0)
HOLD SETTINGS (nwe hold … 0)
(1)
(nwe hold - ncs
(ncs rd setup + ncs rd pulse - nrd
ncs rd setup +
t
t
t
t
t
t
(nwe setup -
nwe pulse) *
CPMCK
CPMCK
CPMCK
CPMCK
CPMCK
CPMCK
nwe pulse *
nwe pulse *
nwe setup *
(ncs rd setup + ncs rd pulse)*
ncs rd pulse length * t
nwe hold *
wr hold )*
ncs wr pulse * t
ncs wr pulse * t
ncs wr setup * t
TBD
Min
setup)* t
+ TBD
+ TBD
+ TBD
+ TBD
+ TBD
+ TBD
t
CPMCK
3.3V Supply
TBD
CPMCK
+ TBD
Min
CPMCK
CPMCK
CPMCK
+ TBD
Max
CPMCK
+ TBD
+ TBD
+ TBD
+
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
8549A–CAP–10/08