AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 44

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.3.3
Figure 11-3. Single Master Mode
44
CAP7E
AHB
AT91CAP7E
Serializer Programmability
CAP7E AHB CLK
S0
S1
•
In order to maximize the number of I/O supported, modules that handle the Masters-A/B,
Slaves-A/B and Slaves C/D, are programmable at reset time through the CAP7E Control
module in the FPGA. This programmability allows the user to choose whether or not to use
“all” 10 I/O lines for a single serial configuration. In
configured to handle only 1 AHB interface. For example, if the user wants to use only AHB
master A, then the appropriate serial module will need to be configured by setting the Master
mode configuration in the CAP7E Control module to Single Master Mode, which will improve
the number of bits transferred between shifters and speed-up the transfers between the
CAP7E and FPGA.
Another option is to configure the serial module to handle 2 AHB interfaces in Dual Master
Mode. Here the 10 I/O lines are shared between the 2 AHB (Masters/Slaves).
In this case, the data transfer rate between the CAP7E and the FPGA is reduced, but the
data bandwidth increases because now 2 AHB interfaces are enabled.
Figure 11-4
interface.
CAP7E FSM
Shifter: This block is controlled by the FSM, and it handles all the data shifting
(serializing) between the CAP7E-FPGA and transfers 2 bits per cycle. If the FPIF_SCLK
rate is set @100mhz, then the shifters transfer 200Mbps.
Shifter
shows how the Dual Master Mode uses half of the dedicated I/O for another AHB
FPIF Serial Clock
All I/O lines for S0
Control
FPGA FSM
Shifter
Figure
FPGA AHB CLK
S0
S1
11-3, the serial module is shown
FPGA
AHB
8549A–CAP–10/08