AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 35

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 10-1.
10.3
10.3.1
10.3.2
10.3.3
10.4
8549A–CAP–10/08
Peripheral ID
Peripheral Interrupts and Clock Control
Peripherals Signals Multiplexing on I/O Lines
29
30
31
System Interrupt
External Interrupts
Timer Counter Interrupts
AT91CAP7E Peripheral Identifiers (Continued)
Peripheral Mnemonic
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
The three Timer Counter channels interrupt signals are OR-wired together to provide the inter-
rupt source 7 of the Advanced Interrupt Controller. This forces the programmer to read all Timer
Counter status registers before branching the right Interrupt Service Routine.
The Timer Counter channels clocks cannot be deactivated independently. Switching off the
clock of the Peripheral 7 disables the clock of the 3 channels.
The AT91CAP7E features two PIO controllers, PIOA which multiplexes the I/O lines of the stan-
dard peripheral set and PIOB which multiplexes the FPGA Interface through MPIO.
Each PIO Controller controls up to 32 lines. On PIOA, each line can be assigned to one of two
peripheral functions, A or B. The multiplexing table in the following paragraph define how the I/O
lines of the peripherals A and B are multiplexed on PIOA.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O is listed, the PIO Line resets in input mode with the pull-up enabled, so that the
device is maintained in a static state as soon as the reset is released. As a result, the bit corre-
sponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-Time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
N/A
AIC
AIC
Peripheral Name
Not Available
Advanced Interrupt Controller
Advanced Interrupt Controller
AT91CAP7E
External Interrupt
IRQ0
IRQ1
35