AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 350

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 29-4. Fractional Baud Rate Generator
29.6.1.3
29.6.1.4
350
SCK
Reserved
MCK/DIV
AT91CAP7E
MCK
Baud Rate in Synchronous Mode
Baud Rate in ISO 7816 Mode
USCLKS
0
1
2
3
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the
system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
The ISO7816 specification defines the bit rate with the following formula:
where:
Baudrate
BaudRate
16-bit Counter
CD
=
B
---------------------------------------------------------------- -
⎛
⎝
8 2 Over
Modulus
=
Control
=
(
FP
SelectedClock
------------------------------------- -
Di
----- -
Fi
SelectedClock
–
×
CD
f
) CD
⎛
⎝
glitch-free
USCLKS = 3
+
logic
FP
------ -
FP
8
⎞
⎠
SYNC
⎞
⎠
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
0
1
SYNC
SCK
Baud Rate
Sampling
8549A–CAP–10/08
Clock
Clock