AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 42

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 11-1. .CAP7E and FPGA System Diagram
11.3
42
CAP7E
TIMERS
USART
USART
USB
ADC
SPI
PIO
Functional Description
AT91CAP7E
APB
NVM / SDRAM / SRAM
Note:
The module called “Custom MP” shown inside the FPGA is logic from an RTL template provided
to simplify the integratration of AHB or APB peripherals. Using “Custom MP” will also make a
migration from a CAP7E to a fully customized CAP7 solution much easier since modules are
connected the same way in the wrapper for the CAP7 MP block.
All the RTL for the interface targeted for the FPGA and additional modules such as a HZBT,
AHB/APB bridge, etc. provided by ATMEL contain all the proper constraints for each supported
FPGA vendor. Additional customer-specific logic can also be added to the FPGA.
The FPGA Interface includes logic that encodes or decodes the internal AHB transactions.
The encoded/decoded data is transferred through MPIO’s using dedicated serializers for
each master and slave. Due to the large number of bits to be transferred, a single transfer
will take several AHB clock cycles. The specific number of clock cycles depends on the ratio
between the CAP7E MCK and FPIF_SCLK and the ratio between the FPGA AHB clock and
the FPIF_SCLK. The lower those two ratios are, the fewer AHB clocks it will take for a single
transfer.
64KB SRAM
ARM7TDMI
96KB SRAM
The external ZBT-RAM and NVM/SDRAM/SRAM are optional, based on applications and system
requirements
INTERFACE
EBI
FPGA
RAM
ZBT
FPGA
Additional NON-AHB/APB Logic
CAP7E-Ctrol
HZBT
AHB’s
PDC
14 APB’s Slaves
2 PDC Channels
2 AHB Masters
Custom MP
4 AHB Slaves
IRQ
8549A–CAP–10/08