AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 364
![MCU CAP7 FPGA 225LFBGA](/photos/12/32/123241/225-lfbga_sml.jpg)
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 29-23. Timeguard Operations
29.6.3.11
364
Baud Rate
TXEMPTY
US_THR
TXRDY
Clock
Write
TXD
AT91CAP7E
Receiver Time-out
Start
Bit
D0
D1
Table 29-7
in relation to the function of the Baud Rate.
Table 29-7.
The Receiver Time-out provides support in handling variable-length frames. This feature detects
an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel
Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an
end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at
0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR
remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO.
This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user
can either:
D2
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state
D3
D4
D5
Baud Rate
indicates the maximum length of a timeguard period that the transmitter can handle
115200
Bit/sec
14400
19200
28800
33400
56000
57600
1 200
9 600
D6
Maximum Timeguard Length Depending on Baud Rate
D7
Parity
Bit
Stop
Bit
TG = 4
Start
Bit
D0
Bit time
69.4
52.1
34.7
29.9
17.9
17.4
833
104
8.7
μs
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Timeguard
212.50
26.56
17.71
13.28
8.85
7.63
4.55
4.43
2.21
ms
TG = 4
8549A–CAP–10/08
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