AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 515

• Manufacturer Part Number: AT91CAP7E-NA-ZJ
• Description: MCU CAP7 FPGA 225LFBGA
• Manufacturer: Atmel
• Series: CAP™r

Specifications of AT91CAP7E-NA-ZJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: ROM
• Ram Size: 160K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8549A–CAP–10/08
28 Serial Peripheral Interface (SPI) ......................................................... 315
29 Universal Synchronous Asynchronous Receiver Transmitter (USART)
343
28.1Description ..........................................................................................................315
28.2Block Diagram .....................................................................................................316
28.3Application Block Diagram ..................................................................................317
28.4Signal Description ..............................................................................................317
28.5Product Dependencies ........................................................................................317
28.9Functional Description .........................................................................................318
28.14Serial Peripheral Interface (SPI) User Interface ................................................329
29.1Description ..........................................................................................................343
29.2Block Diagram .....................................................................................................344
29.3Application Block Diagram ..................................................................................345
29.4I/O Lines Description ..........................................................................................345
27.37.17PIO Controller Interrupt Status Register 308
27.38.18PIO Multi-driver Enable Register 308
27.39.19PIO Multi-driver Disable Register 309
27.40.20PIO Multi-driver Status Register 309
27.41.21PIO Pull Up Disable Register 310
27.42.22PIO Pull Up Enable Register 310
27.43.23PIO Pull Up Status Register 311
27.44.24PIO Peripheral A Select Register 311
27.45.25PIO Peripheral B Select Register 312
27.46.26PIO Peripheral A B Status Register 312
27.47.27PIO Output Write Enable Register 313
27.48.28PIO Output Write Disable Register 313
27.49.29PIO Output Write Status Register 314
28.6.1I/O Lines 317
28.7.2Power Management 317
28.8.3Interrupt 318
28.10.1Modes of Operation 318
28.11.2Data Transfer 319
28.12.3Master Mode Operations 320
28.13.4SPI Slave Mode 328
28.15.1SPI Control Register 330
28.16.2SPI Mode Register 331
28.17.3SPI Receive Data Register 332
28.18.4SPI Transmit Data Register 334
28.19.5SPI Status Register 335
28.20.6SPI Interrupt Enable Register 337
28.21.7SPI Interrupt Disable Register 338
28.22.8SPI Interrupt Mask Register 339
28.23.9SPI Chip Select Register 340
AT91CAP7E
515