C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 11

• Manufacturer Part Number: C8051F930-GQ
• Description: IC 8051 MCU 64K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F930-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 23x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F930DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 23-ch x 10-bit
• No. Of I/o's: 24
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1466

22. SMBus
23. UART0
24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)
25. Timers
26. Programmable Counter Array
Figure 21.2. Port I/O Cell Block Diagram ............................................................... 213
Figure 21.3. Crossbar Priority Decoder with No Pins Skipped ............................... 217
Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 218
Figure 22.1. SMBus Block Diagram ....................................................................... 233
Figure 22.2. Typical SMBus Configuration ............................................................. 234
Figure 22.3. SMBus Transaction ............................................................................ 235
Figure 22.4. Typical SMBus SCL Generation......................................................... 238
Figure 22.5. Typical Master Write Sequence ......................................................... 247
Figure 22.6. Typical Master Read Sequence ......................................................... 248
Figure 22.7. Typical Slave Write Sequence ........................................................... 249
Figure 22.8. Typical Slave Read Sequence ........................................................... 250
Figure 23.1. UART0 Block Diagram ....................................................................... 255
Figure 23.2. UART0 Baud Rate Logic .................................................................... 256
Figure 23.3. UART Interconnect Diagram .............................................................. 257
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 257
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 258
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 259
Figure 24.1. SPI Block Diagram ............................................................................. 263
Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 266
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Figure 24.5. Master Mode Data/Clock Timing ........................................................ 268
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 269
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 269
Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 275
Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 275
Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 276
Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 276
Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 281
Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 282
Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 283
Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 288
Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 289
Figure 25.6. Timer 2 Capture Mode Block Diagram ............................................... 290
Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 294
Figure 25.8. Timer 3 8-Bit Mode Block Diagram. ................................................... 295
Figure 25.9. Timer 3 Capture Mode Block Diagram ............................................... 296
Figure 26.1. PCA Block Diagram............................................................................ 300
Connection Diagram .............................................................................. 266
Connection Diagram .............................................................................. 266
Rev. 0.2
C8051F93x-C8051F92x
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