C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 183

• Manufacturer Part Number: C8051F930-GQ
• Description: IC 8051 MCU 64K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F930-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 23x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F930DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 23-ch x 10-bit
• No. Of I/o's: 24
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1466

Important Notes:
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SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control
SFR Page = 0x0; SFR Address = 0xFF
Reset
Name
Bit
4:2
1:0
Type
7
6
5
Bit
The Power-on Reset (POR) delay is not incurred after a VDD/DC+ supply monitor reset. See Section
“4. Electrical Characteristics” on page 43 for complete electrical characteristics of the VDD/DC+ moni-
tor.
Software should take care not to inadvertently disable the V
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the V
The VDD/DC+ supply monitor must be enabled before selecting it as a reset source . Selecting the
VDD/DC+ supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD/DC+ supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 43 for minimum VDD/DC+ Supply Monitor turn-on time. No delay should be introduced in
systems where software contains routines that erase or write Flash memory. The procedure for
enabling the VDD/DC+ supply monitor and selecting it as a reset source is shown below: 
1. Enable the VDD/DC+ Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD/DC+ Supply Monitor to stabilize (optional).
3. Select the VDD/DC+ Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
VDDSTAT
Reserved
VDMEN
VDDOK
Unused
VDMEN
Name
R/W
7
1
VDDSTAT
VDD/DC+ Supply Monitor Enable.
This bit turns the VDD/DC+ supply monitor circuit on/off. The VDD/DC+ Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD/DC+ Supply Monitor Disabled.
1: VDD/DC+ Supply Monitor Enabled.
VDD/DC+ Supply Status.
This bit indicates the current power supply status.
0: VDD/DC+ is at or below the V
1: VDD/DC+ is above the V
VDD/DC+ Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD/DC+ is at or below the V
1: VDD/DC+ is above the V
Reserved.
Read = 000b. Must Write 000b.
Unused.
Read = 00b. Write = Don’t Care.
Varies
R
6
VDDOK
Varies
R
5
DD
Reserved
Monitor enabled as a reset source.
R/W
Rev. 1.1
RST
WARN
4
0
threshold.
RST
WARN
monitor threshold.
C8051F93x-C8051F92x
Reserved
Function
threshold.
R/W
threshold.
3
0
DD
Monitor as a reset source when writing
Reserved
R/W
2
0
R/W
1
0
R/W
0
0
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