C8051F930-GQ Silicon Laboratories Inc, C8051F930-GQ Datasheet - Page 291

• Manufacturer Part Number: C8051F930-GQ
• Description: IC 8051 MCU 64K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F930-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 23x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F930DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 23-ch x 10-bit
• No. Of I/o's: 24
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1478 - PLATFORM PROG TOOLSTCK F920,F930336-1477 - PLATFORM PROG TOOLSTCK F920,F930336-1473 - KIT DEV C8051F920,F921,F930,F931336-1472 - BOARD TARGET/PROTO W/C8051F930
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1466

SFR Definition 25.8. TMR2CN: Timer 2 Control
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable
Reset
Name
Bit
1:0
Type
7
6
5
4
3
2
Bit
T2XCLK[1:0]
TF2CEN
T2SPLIT
TF2LEN
Name
TF2H
TF2H
TF2L
TR2
R/W
7
0
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts
are also enabled, an interrupt will be generated when the low byte of Timer 2 over-
flows.
Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode.
Timer 2 Split Mode Enable.
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,
Timer 2 operates in 16-bit auto-reload mode.
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
Timer 2 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.
TF2L
R/W
0
6
TF2LEN
R/W
5
0
TF2CEN
R/W
Rev. 1.1
4
0
C8051F93x-C8051F92x
T2SPLIT
Function
R/W
3
0
TR2
R/W
2
0
1
0
T2XCLK[1:0]
R/W
0
0
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