DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet
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DF38602RFT10 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/38602R Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details ...
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Rev. 3.00 May 15, 2007 Page ii of xxxii ...
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Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/38602R Group consists of single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is ...
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Notes: When using an on-chip emulator (E7) for H8/38602R program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7, and cannot be used. 2. Area H'4000 to H'4FFF should not be ...
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Application notes: Document Title F-ZTAT Microcomputer On-Board Programming All trademarks and registered trademarks are the property of their respective owners. Rev. 3.00 May 15, 2007 Page viii of xxxii Document No. REJ05B0523 ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Internal Block Diagram.......................................................................................................... 2 1.3 Pin Assignment ...................................................................................................................... 3 1.4 Pin Functions ......................................................................................................................... 4 Section 2 CPU........................................................................................................7 2.1 Address Space and Memory Map .......................................................................................... 8 2.2 Register Configuration........................................................................................................... 9 2.2.1 General Registers.................................................................................................... 10 ...
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Register Descriptions........................................................................................................... 46 3.4.1 Interrupt Edge Select Register (IEGR) ................................................................... 47 3.4.2 Interrupt Enable Register 1 (IENR1) ...................................................................... 48 3.4.3 Interrupt Enable Register 2 (IENR2) ...................................................................... 49 3.4.4 Interrupt Flag Register 1 (IRR1)............................................................................. 50 3.4.5 Interrupt Flag Register 2 ...
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Notes on Board Design ........................................................................................... 74 4.5.3 Definition of Oscillation Stabilization Wait Time .................................................. 74 4.5.4 Note on Subclock Stop State................................................................................... 76 4.5.5 Note on the Oscillation Stabilization of Resonators ............................................... 76 4.5.6 Note on Using Power-On Reset .............................................................................. ...
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Erase Block Register 1 (EBR1) ............................................................................ 103 6.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 103 6.2.5 Flash Memory Enable Register (FENR)............................................................... 104 6.3 On-Board Programming Modes......................................................................................... 104 6.3.1 Boot Mode ............................................................................................................ 105 6.3.2 Programming/Erasure in User Program Mode...................................................... 108 ...
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Port 9.................................................................................................................................. 132 8.4.1 Port Data Register 9 (PDR9)................................................................................. 133 8.4.2 Port Control Register 9 (PCR9) ............................................................................ 133 8.4.3 Port Open-Drain Control Register 9 (PODR9) ..................................................... 134 8.4.4 Port Pull-Up Control Register 9 (PUCR9)............................................................ 134 8.4.5 Pin Functions ........................................................................................................ ...
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Timer Counter (TCNT)......................................................................................... 164 10.3.8 General Registers (GRA to GRD)............................................................. 165 10.4 Operation ........................................................................................................................... 166 10.4.1 Normal Operation ................................................................................................. 166 10.4.2 PWM Operation.................................................................................................... 170 10.5 Operation Timing............................................................................................................... 175 10.5.1 TCNT Count Timing ............................................................................................ 175 10.5.2 Output ...
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Register Descriptions ......................................................................................................... 202 12.2.1 Timer Control/Status Register WD1 (TCSRWD1)............................................... 203 12.2.2 Timer Control/Status Register WD2 (TCSRWD2)............................................... 205 12.2.3 Timer Counter WD (TCWD)................................................................................ 206 12.2.4 Timer Mode Register WD (TMWD) .................................................................... 207 12.3 Operation ........................................................................................................................... 208 12.3.1 Watchdog Timer ...
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Receive Data Register (RDR)............................................................................... 234 14.3.3 Transmit Shift Register (TSR) .............................................................................. 234 14.3.4 Transmit Data Register (TDR).............................................................................. 234 14.3.5 Serial Mode Register (SMR) ................................................................................ 235 14.3.6 Serial Control Register (SCR) .............................................................................. 237 14.3.7 Serial Status Register (SSR) ................................................................................. 240 ...
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Section 15 Synchronous Serial Communication Unit (SSU) ............................283 15.1 Features.............................................................................................................................. 283 15.2 Input/Output Pins ............................................................................................................... 284 15.3 Register Descriptions ......................................................................................................... 285 15.3.1 SS Control Register H (SSCRH) .......................................................................... 285 15.3.2 SS Control Register L (SSCRL) ........................................................................... 287 15.3.3 SS Mode ...
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Operation ........................................................................................................................... 328 2 16.4 Bus Format...................................................................................................... 328 16.4.2 Master Transmit Operation................................................................................... 329 16.4.3 Master Receive Operation .................................................................................... 331 16.4.4 Slave Transmit Operation ..................................................................................... 333 16.4.5 Slave Receive Operation....................................................................................... 336 16.4.6 Clock Synchronous Serial Format ........................................................................ 337 ...
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Register Descriptions ......................................................................................................... 362 18.3.1 Compare Control Registers 0, 1 (CMCR0, CMCR1) ........................................... 362 18.3.2 Compare Data Register (CMDR).......................................................................... 364 18.4 Operation ........................................................................................................................... 365 18.4.1 Operation Sequence .............................................................................................. 365 18.4.2 Hysteresis Characteristics of Comparator............................................................. 366 18.4.3 Interrupt Setting .................................................................................................... ...
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Output Load Circuit ........................................................................................................... 440 21.7 Recommended Resonators................................................................................................. 440 21.8 Usage Note......................................................................................................................... 441 Appendix ......................................................................................................... 443 A. Instruction Set .................................................................................................................... 443 A.1 Instruction List...................................................................................................... 443 A.2 Operation Code Map............................................................................................. 458 A.3 Number of Execution States ................................................................................. 461 A.4 Combinations ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8/38602R Group .............................................................. 2 Figure 1.2 Pin Assignment of H8/38602R Group (TNP-32) .......................................................... 3 Figure 1.3 Pin Assignment of H8/38602R Group (32P6U-A)........................................................ 3 Section 2 CPU Figure 2.1 Memory Map................................................................................................................. 8 ...
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Figure 4.7 Pin Connection when not Using Subclock .................................................................. 69 Figure 4.8 Pin Connection when Inputting External Clock .......................................................... 70 Figure 4.9 Example of Crystal and Ceramic Resonator Assignment............................................ 72 Figure 4.10 Negative Resistance Measurement and Circuit Modification Suggestions ............... ...
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Figure 10.10 PWM Mode Example (2) ...................................................................................... 171 Figure 10.11 Buffer Operation Example (Output Compare) ...................................................... 172 Figure 10.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 173 Figure 10.13 PWM Mode ...
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Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............ 254 Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 258 Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode ...
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Section Bus Interface 2 (IIC2) Figure 16.1 Block Diagram of I Figure 16.2 External Circuit Connections of I/O Pins ................................................................ 313 2 Figure 16 Bus Formats ...................................................................................................... 328 2 Figure 16 Bus ...
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Section 21 Electrical Characteristics Figure 21.1 Power Supply Voltage and Oscillation Frequency Range (1) ................................. 386 Figure 21.2 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 387 Figure 21.3 Power Supply Voltage and Operating Frequency Range (1)................................... 388 Figure ...
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Figure B.1 (c) Port 1 Block Diagram (P10)................................................................................ 475 Figure B.2 (a) Port 3 Block Diagram (P32)................................................................................ 476 Figure B.2 (b) Port 3 Block Diagram (P31)................................................................................ 477 Figure B.2 (c) Port 3 Block Diagram (P30)................................................................................ 478 Figure B.3 (a) Port ...
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Rev. 3.00 May 15, 2007 Page xxviii of xxxii ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 4 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 16 Table 2.2 Data Transfer Instructions....................................................................................... 17 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 18 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 19 ...
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Table 6.5 Additional-Program Data Computation Table ...................................................... 111 Table 6.6 Programming Time ............................................................................................... 111 Table 6.7 Flash Memory Operating States............................................................................ 115 Section 9 Timer B1 Table 9.1 Timer B1 Operating Modes .................................................................................. 151 Section 10 Timer W Table 10.1 Timer ...
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Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (4)...................................................... 247 Table 14.4 Relation between n and Clock .............................................................................. 248 Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 248 ...
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Table 21.9 Watchdog Timer Characteristics........................................................................... 407 Table 21.10 Power-On Reset Circuit Characteristics ............................................................... 408 Table 21.11 Flash Memory Characteristics .............................................................................. 409 Table 21.12 Absolute Maximum Ratings ................................................................................. 411 Table 21.13 DC Characteristics ................................................................................................ 419 Table 21.14 Control Signal Timing .......................................................................................... ...
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Features • High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions • Various peripheral functions RTC (can be used ...
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Section 1 Overview • Compact package Package Code P-VQFN-32 TNP-32 P-LQFP-32 32P6U-A 1.2 Internal Block Diagram E7_0 X1 E7_1 E7_2 X2 OSC1 OSC2 P10/AEVH/FTIOA/TMOW/CLKOUT P11/AEVL/FTCI (/IRQ1) P12/IRQAEC/AECPWM P30/SCK3/VC (/IRQ0) ref P31/RXD3/IrRXD P32/TXD3/IrTXD Notes: 1. The NMI pin is not available ...
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Pin Assignment P30/SCK3/VC (/IRQ0) ref PB5/AN5/COMP1 PB4/AN4/COMP0 PB3/AN3 PB2/AN2 PB1/AN1/IRQ1 PB0/AN0/IRQ0 Figure 1.2 Pin Assignment of H8/38602R Group (TNP-32) P31/RXD3/IrRXD P30/SCK3/VC (/IRQ0) ref PB5/AN5/COMP1 PB4/AN4/COMP0 PB3/AN3 PB2/AN2 PB1/AN1/IRQ1 PB0/AN0/IRQ0 Figure 1.3 Pin Assignment of H8/38602R Group (32P6U- ...
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Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Type Symbol Pin No. I/O Power Vcc 8 supply pins Vss 6 AVcc 1 Clock pins OSC1 7 OSC2 CLKOUT 13 RES System 4 control ...
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Type Symbol Pin No. I/O NMI Interrupt pins 16 IRQ0 32 (22, 26) IRQ1 31 (14, 23) IRQAEC 15 Timer W FTCI 14 FTIOA FTIOD 10 Asynchro- AEVL 14 nous event AEVH 13 counter AECPWM 15 (AEC) ...
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Section 1 Overview Type Symbol Pin No. I/O A/D AN0 converter AN5 27 ADTRG 9 Comparators COMP0 28 COMP1 27 VCref 26 I/O ports P10 to P12 P30 to P32 P82 ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward compatible with the H8/300 CPU, and supports only normal mode, which has a 64-Kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object ...
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Section 2 CPU • Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 64 Kbytes, which includes the program area and the data area. Figure 2.1 shows ...
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Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR). ...
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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
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General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area. ...
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Section 2 CPU Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W Rev. ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: ...
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Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined ...
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Table 2.2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd ...
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and ...
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Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ...
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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...
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Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result ...
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Table 2.7 Branch Instructions Instruction Size Function Bcc* Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. (EAs) → CCR LDC B/W Moves the ...
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Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B else next; ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows ...
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Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU ...
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Section 2 CPU Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and E0 ...
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The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Immediate—#xx:8, ...
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Section 2 CPU Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ...
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Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Effective Address Calculation PC contents ...
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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ subclock (φ edge of φ or φ to the next rising edge is called one state. A bus cycle consists of two ...
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On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing ...
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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. For the program ...
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Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to ...
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Section 2 CPU 2.8.3 Bit-Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte ...
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Example 2: When the BSET instruction is executed for port 5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level ...
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Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a ...
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Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. ...
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Section 2 CPU • Prior to executing BCLR instruction MOV.B #H'3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 • BCLR ...
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Section 3 Exception Handling Exception handling is caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts after the reset state is cleared by a negation of the ...
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Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table ...
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Source Origin Exception Sources WDT WDT overflow (interval timer) Asynchronous Asynchronous event counter event counter overflow Timer B1 Overflow Synchronous serial Overrun error (SSU) communication unit Transmit data empty (SSU) (SSU)/ Transmit end (SSU) Receive data full (SSU) Conflict error ...
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Section 3 Exception Handling 3.2 Reset A reset has the highest exception priority. There are three sources to generate a reset. Table 3.2 lists the reset sources. Table 3.2 Reset Sources Reset Source RES pin Power-on reset circuit Watchdog timer ...
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RES φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Exception Handling Sequence 3.2.2 Interrupt Immediately ...
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Section 3 Exception Handling 3.3 Input/Output Pins Table 3.3 shows the pin configuration of the interrupt controller. Table 3.3 Pin Configuration Name I/O NMI Input IRQAEC Input IRQ1 Input IRQ0 Input 3.4 Register Descriptions The interrupt controller has the following ...
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Interrupt Edge Select Register (IEGR) IEGR selects whether interrupt requests of the NMI, ADTRG, IRQ1, and IRQ0 pins are generated at the rising edge or falling edge. Initial Bit Bit Name Value 7 NMIEG 0 ...
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Section 3 Exception Handling 3.4.2 Interrupt Enable Register 1 (IENR1) IENR1 enables the RTC, IRQAEC, IRQ1, and IRQ0 interrupts. Initial Bit Bit Name Value 7 IENRTC 0 All 0 2 IENEC2 0 1 IEN1 0 0 ...
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Interrupt Enable Register 2 (IENR2) IENR2 enables the A/D converter, timer B1, and asynchronous event counter interrupts. Initial Bit Bit Name Value IENAD 0 All 0 2 IENTB1 0 1 ...
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Section 3 Exception Handling 3.4.4 Interrupt Flag Register 1 (IRR1) IRR1 indicates the IRQAEC, IRQ1, and IRQ0 interrupt request status. Initial Bit Bit Name Value All 0 2 IRREC2 0 1 IRRI1 0 0 IRRI0 0 ...
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Interrupt Flag Register 2 (IRR2) IRR2 indicates the interrupt request status of the A/D converter, timer B1, and asynchronous event counter. Initial Bit Bit Name Value IRRAD 0 All 0 2 ...
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Section 3 Exception Handling 3.5 Interrupt Sources 3.5.1 External Interrupts There are four external interrupts: NMI, IRQAEC, IRQ1, and IRQ0. (1) NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of ...
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Internal Interrupts Internal interrupts generated from the on-chip peripheral modules have the following features: • For each on-chip peripheral module, there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these ...
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Section 3 Exception Handling External or internal interrupts External interrupts or internal interrupt enable signals Figure 3.2 Block Diagram of Interrupt Controller Rev. 3.00 May 15, 2007 Page 54 of 516 REJ09B0152-0300 Interrpt controller Interrupt request I CCR (CPU) ...
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Program execution state No NMI Yes IRRI0 = 1 Yes IEN0 = 1 Yes Yes PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine [Legend] PC: Program counter CCR: Condition code register ...
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Section 3 Exception Handling 3.6.1 Interrupt Exception Handling Sequence Figure 3.4 shows the interrupt exception handling sequence. The example shown is for the case where the program area and stack area are in a 16-bit and 2-state access space. Figure ...
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Stack Status after Exception Handling Figures 3.5 shows the stack after completion of interrupt exception handling. SP – – – – (R7) Stack area Prior to start of interrupt exception handling ...
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Section 3 Exception Handling 3.8 Usage Notes 3.8.1 Notes on Stack Area Use When word data is accessed in this LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in ...
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Notes on Switching Functions of External Interrupt Pins When PFCR and PMRB are rewritten to switch the functions of external interrupt pins and when the value of the ECPWME bit in AEGSR is rewritten to switch between selection and ...
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Section 3 Exception Handling 3.8.3 Method for Clearing Interrupt Request Flags Use the recommended method given below when clearing the flags in interrupt request registers (IRR1 and IRR2). • Recommended method Use a single instruction to clear flags. The bit ...
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Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. When an interrupt request is generated, an interrupt is requested to the CPU. At that time, if the CPU is executing an instruction that ...
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Section 3 Exception Handling Rev. 3.00 May 15, 2007 Page 62 of 516 REJ09B0152-0300 ...
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Section 4 Clock Pulse Generators The clock pulse generator is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, system clock divider, and on-chip ...
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Section 4 Clock Pulse Generators 4.1 Register Description • Oscillator control register (OSCCR) 4.1.1 Oscillator Control Register (OSCCR) OSCCR controls the subclock oscillator, on-chip feedback resistance, and on-chip oscillator. Initial Bit Bit Name Value 7 SUBSTP 0 6 RFCUT 0 ...
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Initial Bit Bit Name Value All 0 * 1 OSCF Note: The value depends on the state of the E7_2 pin. Refer to table 4.1. * R/W Description Reserved These ...
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Section 4 Clock Pulse Generators 4.2 System Clock Oscillator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Either the system clock oscillator or on-chip ...
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External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.4 shows a typical connection. The duty cycle of the external clock signal must 55%. Figure 4.4 Example ...
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Section 4 Clock Pulse Generators 4.3 Subclock Oscillator A subclock can be provided by connecting a crystal resonator or inputting an external clock. Either the subclock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. For the ...
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Figure 4.6 shows the equivalent circuit of the crystal resonator. X1 Figure 4.6 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator 4.3.2 Pin Connection when not Using Subclock When the subclock is not used, connect the X1 pin to GND and leave ...
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Section 4 Clock Pulse Generators 4.3.3 External Clock Input Method Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4. Figure 4.8 Pin Connection when Inputting External Clock Frequency ...
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Prescalers This LSI is equipped with two on-chip prescalers (prescaler S and prescaler W), which have different input clocks. Prescaler 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal ...
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Section 4 Clock Pulse Generators 4.5 Usage Notes 4.5.1 Note on Resonators and Resonator Circuits Resonator characteristics are closely related to board design. Therefore, resonators should be assigned after being carefully evaluated by the user in the masked ROM version ...
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Figure 4.10 (1) shows an example measuring circuit with the negative resistance recommended by the resonator manufacturer. Note that if the negative resistance of the circuit is less than that recommended by the resonator manufacturer, it may be difficult to ...
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Section 4 Clock Pulse Generators 4.5.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed ...
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Wait Time After the system clock is generated, the time required for the amplitude of the oscillation waveform to increase, the oscillation frequency to stabilize, and the CPU and peripheral functions to begin operating. Oscillation waveform (OSC2) System clock ...
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Section 4 Clock Pulse Generators 4.5.4 Note on Subclock Stop State To stop the subclock, a state transition should not be made except to mode in which the system clock operates. If the state transition is made to other mode, ...
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Section 5 Power-Down Modes This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by ...
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Section 5 Power-Down Modes 5.1 Register Descriptions The registers related to power-down modes are as follows. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2) 5.1.1 System ...
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Initial Bit Bit Name Value 3 LSON 0 2 TMA3 0 1 MA1 1 0 MA0 1 Table 5.1 Operating Frequency and Waiting Time Bit STS2 STS1 STS0 Waiting States 8,192 states 1 16,384 states 1 0 ...
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Section 5 Power-Down Modes 5.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Bit Name Value All 1 4 NESEL 1 3 DTON 0 2 MSON 0 1 ...
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Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter the standby state in module units. • CKSTPR1 Initial Bit Bit Name Value S3CKSTP 0 ...
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Section 5 Power-Down Modes • CKSTPR2 Initial Bit Bit Name Value TWCKSTP 0 5 IICCKSTP SSUCKSTP 3 AECCKSTP 0 2 WDCKSTP COMPCKSTP Notes: 1. When the SCI3 ...
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Mode Transitions and States of LSI Figure 5.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts ...
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Section 5 Power-Down Modes Reset state Program SLEEP halt state instruction Standby mode d SLEEP instruction 4 e SLEEP instruction SLEEP instruction Watch 1 mode : Transition is made after exception handling is executed. Mode Transition Conditions (1) LSON MSON ...
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Table 5.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling LSON MSON SSBY Active (high speed) mode ...
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Section 5 Power-Down Modes Table 5.3 Internal State in Each Operating Mode Active Mode High- Function speed System clock oscillator Functions Subclock oscillator Functions/ Halted CPU Instructions Functions RAM Registers I/O External NMI Functions interrupts IRQ0 IRQ1 IRQAEC Peripheral Timer ...
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Functions if φ , φ otherwise. 4. Functions if the on-chip oscillator is selected. Halted and retained otherwise. 5. Functions if the on-chip oscillator is selected or if φ internal clock. Halted and retained otherwise. 6. Functions ...
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Section 5 Power-Down Modes 5.2.2 Standby Mode In standby mode, the system clock oscillator stops, and the CPU and on-chip peripheral modules stop functioning except for the WDT, asynchronous event counter, and comparators. However, as long as the rated voltage ...
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Subsleep Mode In subsleep mode, the CPU operation stops but on-chip peripheral modules function except for the IIC2. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the ...
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Section 5 Power-Down Modes 5.2.6 Active (Medium-Speed) Mode In active (medium-speed) mode, the clock set by the MA1 and MA0 bits in SYSCR1 is used as the system clock, and the CPU and on-chip peripheral modules function. Active (medium-speed) mode ...
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Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is made between these two modes without stopping program execution. A direct transition can also be made when the operating clock is ...
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Section 5 Power-Down Modes 5.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON ...
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Direct Transition from Active (Medium-Speed) Mode to Subactive Mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is ...
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Section 5 Power-Down Modes 5.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 ...
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Notes on External Input Signal Changes before/after Direct Transition • Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External Input Signal Changes before/after Standby ...
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Section 5 Power-Down Modes 5.4 Module Standby Function The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral ...
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Usage Notes 5.6.1 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while the SSBY and TMA3 bits in SYSCR1 and the LSON bit in SYSCR1 are cleared ...
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Section 5 Power-Down Modes (2) When External Input Signals cannot be Captured because Internal Clock Stops The case of falling edge capture is shown in figure 5.3. As shown in the case marked "Capture not possible," when an external input ...
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The features of the 16-Kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. • Programming/erasing methods The flash memory is programmed 128 bytes at a time. Erasure is performed in single-block units. The flash memory is ...
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Section 6 ROM 6.1 Block Configuration Figure 6.1 shows the block configuration of flash memory. The thick lines indicate erasing a block, the narrow lines indicate programming units, and the values are addresses. The 16-Kbyte flash memory is divided into ...
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Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory power control register (FLPWCR) • Flash memory ...
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Section 6 ROM Initial Bit Bit Name Value 6.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that indicates the state of flash memory programming/erasure. FLMCR2 ...
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Erase Block Register 1 (EBR1) EBR1 specifies the erase block of flash memory. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...
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Section 6 ROM 6.2.5 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR. Initial Bit Bit Name Value 7 FLSHE 0 ...
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Boot Mode Table 6.2 shows the boot mode operations between a reset released and a branch to the programming control program. This LSI includes a system clock oscillator which is operated by a resonator or an external clock and ...
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Section 6 ROM 6. Before branching to the programming control program, this LSI terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR3 to 0), however the adjusted bit rate value remains set in BRR. Therefore, ...
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Table 6.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...
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Section 6 ROM Table 6.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps MHz 4,800 bps MHz 2,400 ...
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Flash Memory Programming/Erasure A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: ...
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Section 6 ROM 8. The maximum number of repetitions of the programming/programming-verifying sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse Enable WDT Set PSU bit to 1 Wait 50 µs Set P bit to ...
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Table 6.4 Reprogramming Data Computation Table Programming Data Verifying Data Table 6.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table 6.6 Programming Time ...
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Section 6 ROM 6.4.2 Erasing/Erasing-Verifying When erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 6.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasure is performed in block units. Select a ...
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Set block start address to verifying address Dummy write H'FF to verifying address Increment address No No Note: *The RTS instruction must not be used during a period from dummy-writing of H' verifying address until reading verifying data ...
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Section 6 ROM 6.5 Programming/Erasing Protection There are three types of flash memory programming/erasing protection; hardware protection, software protection, and error protection. 6.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled ...
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The FLMCR1, FLMCR2, and EBR1 settings are retained, however programming mode or erasing mode is aborted when the error occurred. Programming mode or erasing mode cannot be re- entered by re-setting the bit. However, settings of the ...
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Section 6 ROM 6.7 Notes on Setting Module Standby Mode When the flash memory is set to enter the module standby mode, the system clock supply is stopped to the module, the function is stopped, and the state is the ...
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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/38602RF Masked ...
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Section 7 RAM Rev. 3.00 May 15, 2007 Page 118 of 516 REJ09B0152-0300 ...
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The H8/38602R Group has 13 general I/O ports and six general input-only ports. Port large current port, which can drive 15 mA (@V these ports can become an input port immediately after a reset. They can also ...
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Section 8 I/O Ports 8.1.1 Port Data Register 1 (PDR1) PDR1 is a register that stores data of port 1. Initial Bit Bit Name Value P12 0 1 P11 0 0 P10 0 8.1.2 ...
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Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS of the port 1 pins in bit units. Initial Bit Bit Name Value PUCR12 0 1 PUCR11 0 0 PUCR10 0 8.1.4 ...
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Section 8 I/O Ports Initial Bit Bit Name Value 2 CLKOUT 0 1 TMOW 0 0 AEVH 0 [Legend] x: Don't care. Note: When the IRQ1S1 and IRQ1S0 bits in PFCR are set to B'10, the pin function becomes * ...
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P11/AEVL/FTCI (/IRQ1) pin Register Name PFCR Bit Name IRQ1S1 and IRQ1S0 Setting Other than B'10 B'10 [Legend] x: Don't care. • P10/AEVH/FTIOA/TMOW/CLKOUT pin Register Name PMR1 Bit Name CLKOUT TMOW AEVH IOA2 IOA1 IOA0 PCR10 Setting 0 1 [Legend] ...
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Section 8 I/O Ports 8.1.6 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on ...
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Port Data Register 3 (PDR3) PDR3 is a register that stores data of port 3. Initial Bit Bit Name Value P32 0 1 P31 0 0 P30 0 8.2.2 Port Control Register 3 ...
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Section 8 I/O Ports 8.2.3 Port Pull-Up Control Register 3 (PUCR3) PUCR3 controls the pull-up MOS of the port 3 pins in bit units. Initial Bit Bit Name Value PUCR32 0 1 PUCR31 0 ...
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Pin Functions The relationship between the register settings and the port functions is shown below. • P32/TXD3/IrTXD pin Register Name SPCR Bit Name SPC3 Setting 0 1 [Legend] x: Don't care. • P31/RXD3/IrRXD pin Register Name SCR3 Bit Name ...
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Section 8 I/O Ports 8.2.6 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on ...
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Port Data Register 8 (PDR8) PDR8 is a register that stores data of port 8. Initial Bit Bit Name Value P84 0 3 P83 0 2 P82 0 8.3.2 ...
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Section 8 I/O Ports 8.3.3 Port Pull-Up Control Register 8 (PUCR8) PUCR8 controls the pull-up MOS of the port 8 pins in bit units. Initial Bit Bit Name Value PUCR84 0 3 PUCR83 0 ...
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P83/FTIOC pin Register Name TMRW Bit Name PWMC Setting 0 1 [Legend] x: Don't care. • P82/FTIOB pin Register Name TMRW Bit Name PWMB Setting 0 1 [Legend] x: Don't care. TIOR1 IOC2 IOC1 IOC0 ...
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Section 8 I/O Ports 8.3.5 Input Pull-Up MOS Port 8 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR8 bit is cleared to 0, setting the corresponding PUCR8 bit to 1 turns on ...
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Port Data Register 9 (PDR9) PDR9 is a register that stores data of port 9. Initial Bit Bit Name Value P93 0 2 P92 0 1 P91 0 0 P90 0 8.4.2 Port ...
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Section 8 I/O Ports 8.4.3 Port Open-Drain Control Register 9 (PODR9) PODR9 selects the output format for port 9 pins. Initial Bit Bit Name Value P93ODR 0 2 P92ODR 0 1 P91ODR 0 0 ...
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Pin Functions The relationship between the register settings and the port functions is shown below. Note on the followings when port 9 is used. 1. When IIC is used, SSU should not be set. 2. When SSU is used, ...
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Section 8 I/O Ports • P92/SSO (/IRQ0) pin Register Name Bit Name IRQ0S1 and IRQ0S0 Setting Other than B'01 B'01 [Legend] x: Don't care. Note: When this pin is used as the SSO/SSCK pin, register settings of the SSU are ...
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P90/SCS/SCL pin Register Name Bit Name Setting [Legend] x: Don't care. Note: When this pin is used as the SCS/SSI pin, register settings of the SSU are required. For details, see section 15.4.4, Communication Modes and Pin Functions, and ...
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Section 8 I/O Ports 8.5 Port B Port input-only port also functioning as an interrupt input pin, analog input pin, and comparator pin. Figure 8.5 shows its pin configuration. Port B has the following registers. • Port ...
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Port Mode Register B (PMRB) PMRB controls the selection of the port B pin functions. Initial Bit Bit Name Value ADTSTCHG 0 IRQ1 0 0 IRQ0 0 Note: * ...
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Section 8 I/O Ports 8.5.3 Pin Functions The relationship between the register settings and the port functions is shown below. • PB5/AN5/COMP1 pin Register Name AMR Bit Name CH3 to CH0 Setting Other than B'1001 B'1001 [Legend] x: Don't care. ...
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PB1/AN1/IRQ1 pin Register Name PMRB Bit Name IRQ1 Setting 0 1 [Legend] x: Don't care. • PB0/AN0/IRQ0 pin Register Name PMRB Bit Name IRQ0 Setting 0 1 [Legend] x: Don't care. AMR PFCR CH3 to CH0 IRQ1S1 and IRQ1S0 ...
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Section 8 I/O Ports 8.6 Input/Output Data Inversion 8.6.1 Serial Port Control Register (SPCR) SPCR switches input/output data inversion of the RXD3 (IrRXD) and TXD3 (IrTXD) pins. P31/RXD3/IrRXD P32/TXD3/IrTXD Figure 8.6 Input/Output Data Inversion Function Initial Bit Bit Name Value ...
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Initial Bit Bit Name Value 0 SCINV0 0 Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input ...
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Section 8 I/O Ports 8.7 Usage Notes 8.7.1 How to Handle Unused Pin If an I/O pin not used by the user system is floating, pull down. • unused pin is an input pin, handle ...
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Timer 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 9.1 shows a block diagram of timer B1. 9.1 Features • Selection of eight ...
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Section 9 Timer B1 9.2 Register Descriptions Timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 9.2.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload ...
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Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read ...
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Section 9 Timer B1 9.3 Usage Method Figure 9.2 shows the initial setting flow of timer B1 after a reset, and figure 9.3 shows the processing flow for changing a setting during counter operation. Bit TMB16 in TMB1 must be ...
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To modify the counter clock, change the value in bits TMB12 to TMB10 in TMB1 Figure 9.3 Processing Flow When Changing Setting during Counter Operation Clear bit TMB16 in TMB1 stop counter operation (bit TMB16 ...
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Section 9 Timer B1 9.4 Operation 9.4.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to ...
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Timer B1 Operating Modes Table 9.1 shows the timer B1 operating modes. Table 9.1 Timer B1 Operating Modes Active Clock High- Medium- High- Source speed speed speed ο ο ο φw/256, φw/1024 ο ο ο φ/4, φ/16, φ/64, φ/256, ...
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Section 9 Timer B1 Rev. 3.00 May 15, 2007 Page 152 of 516 REJ09B0152-0300 ...
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The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. ...
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Section 10 Timer W Table 10.1 Timer W Functions Item Counter Internal clocks: φ, φ/2, φ/4, φ/8, φ Count clock External clock: FTCI General registers Period (output compare/input specified in capture registers) GRA Counter clearing function GRA compare match Initial ...
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Internal clock: φ/2 φ/4 φ/8 Clock φ W selector φ φ /16 W External clock: FTCI Comparator [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register ...
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Section 10 Timer W 10.2 Input/Output Pins Table 10.2 shows the pin configuration of the timer W. Table 10.2 Pin Configuration Name Abbreviation External clock input FTCI Input capture/output FTIOA compare A Input capture/output FTIOB compare B Input capture/output FTIOC ...
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Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Bit Name Value 7 CTS 0 BUFEB 0 4 BUFEA 0 PWMD 0 ...
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Section 10 Timer W 10.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Bit Name Value 7 CCLR 0 6 CKS2 0 5 CKS1 ...
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Initial Bit Bit Name Value 1 TOB 0 0 TOA 0 [Legend] x: Don't care. Note: The change of the setting is immediately reflected in the output value. * 10.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer ...
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Section 10 Timer W 10.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Bit Name Value 7 OVF 0 All 1 3 IMFD 0 2 IMFC 0 Rev. 3.00 May ...
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Initial Bit Bit Name Value 1 IMFB 0 0 IMFA 0 Note: * Only 0 can be written to clear the flag. 10.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the ...
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Section 10 Timer W Initial Bit Bit Name Value 5 IOB1 0 4 IOB0 0 IOA2 0 1 IOA1 0 0 IOA0 0 [Legend] x: Don't care. Rev. 3.00 May 15, 2007 Page 162 of 516 ...
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Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Initial Bit Bit Name Value IOD2 0 5 IOD1 0 4 ...
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Section 10 Timer W Initial Bit Bit Name Value 1 IOC1 0 0 IOC0 0 [Legend] x: Don't care. 10.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in ...
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General Registers (GRA to GRD) Each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. ...
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Section 10 Timer W 10.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 10.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running ...