DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 537

• Manufacturer Part Number: DF38602RFT10
• Description: MCU 3V 16K 32-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H SLPr

Specifications of DF38602RFT10

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, IrDA, SCI, SSU
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F38602RFT10; HD64F38602RFT10

Item
Section 9 Timer B1
Figure 9.2 Timer B1 Initial Setting
Flow
Section 11 Realtime Clock (RTC)
11.3.7 Clock Source Select
Register (RTCCSR)
11.4.1 Initial Settings of Registers
after Power-On
11.5 Interrupt Sources
11.6.2 Note when Using RTC
Interrupts
Page Revisions (See Manual for Details)
148
193
196
198
199
The RTC registers that store second, minute, hour, and
Modified
Modified
Modified
Modified
day-of-week data, control registers, and interrupt
registers are not reset by a RES input, or by a reset
source caused by a watchdog timer.
… When using an interrupt, set the IENRTC (RTC
interrupt request enable) bit in IENR1 to 1 last after
other registers are set.
Added
Bit Bit Name Description
3
2
1
0
RCS3
RCS2
RCS1
RCS0
Cancel the module standby mode of timer B1
*
1
Clock Source Selection
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000: φ
1001 to 1111: Setting prohibited
Set counter function with bit TMB17
in TMB1 and counter clock with bits
(bit TMB16 must be cleared to 0
TMB12 to TMB10 in TMB1
when writing to these bits)
Rev. 3.00 May 15, 2007 Page 503 of 516
W
/4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
REJ09B0152-0300