DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 374

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
Section 16 I
16.4.7
The logic levels on the SCL and SDA pins are internally latched via noise cancelers. Figure 16.16
shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
16.4.8
Flowcharts in respective modes that use the I
16.20.
Rev. 3.00 May 15, 2007 Page 340 of 516
REJ09B0152-0300
SCL or SDA
input signal
Sampling
clock
2
C Bus Interface 2 (IIC2)
Noise Canceler
Example of Use
Figure 16.16 Block Diagram of Noise Conceler
Sampling clock
D
System clock
period
Latch
C
Q
D
2
C bus interface 2 are shown in figures 16.17 to
Latch
C
Q
Match detector
SCL or SDA
Internal
signal

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