DF38602RFT10 Renesas Electronics America, DF38602RFT10 Datasheet - Page 91

MCU 3V 16K 32-QFN

DF38602RFT10

Manufacturer Part Number
DF38602RFT10
Description
MCU 3V 16K 32-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8/300H SLPr
Datasheet

Specifications of DF38602RFT10

Core Processor
H8/300H
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, IrDA, SCI, SSU
Peripherals
POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F38602RFT10
HD64F38602RFT10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF38602RFT10V
Manufacturer:
Renesas Electronics America
Quantity:
135
3.7
Figures 3.5 shows the stack after completion of interrupt exception handling.
3.7.1
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.4
Note:
Item
Waiting time for completion of executing instruction*
Saving of PC and CCR to stack
Vector fetch
Instruction fetch
Internal processing
*
Interrupt Response Time
Stack Status after Exception Handling
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
[Legend]
PCH:
PCL:
CCR:
SP:
Notes:
Excluding EEPMOV instruction.
Interrupt Wait States
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
2.
* Ignored when returning from the interrupt handling routine.
1.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Prior to start of interrupt
exception handling
Figure 3.5 Stack Status after Exception Handling
Stack area
saved to stack
PC and CCR
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
After completion of interrupt
exception handling
States
1 to 23
4
2
4
4
Rev. 3.00 May 15, 2007 Page 57 of 516
CCR
CCR *
PCH
PCL
Section 3 Exception Handling
Even address
Total
15 to 37
REJ09B0152-0300

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